Electronic – Test point map for BBC micro:bit

First google result for condom electronic testing:

Although DUREX® condoms are now ready for packaging, they will not reach that stage until they have undergone a series of stringent Quality Control tests. This adherence to high quality standards has helped make DUREX® the leading condom brand in the world today. With a product such as a condom, where quality is vitally important to the user, it is essential that every reasonable effort is made to ensure the reliability of DUREX® condoms.

Electronic testing as well as the tests specified by national and international standards, DUREX® condoms are electronically tested. This involves each condom being stretched over a metal former and subjected to a voltage current. Any breakdown of the film is measured and minor flaws, even ones far too small to be detected by the human eye, result in the condom being instantly rejected.

Lifestyles brand:

IV. ELECTRONIC TESTING All condoms are electronically tested for pinholes in the manufacturing area. This is accomplished by subjecting them to a high-voltage test that rejects individual condoms that, due to pinholes, allow current to be conducted across the rubber film.

The latex has insulation properties. If a hole or defect is present, it will not insulate properly, hence rejected.

After studying further i found that -c option can be used even for two files i.e. testbench.v and verilog.v.

we just need to create a ".txt" file with the name of the both the files written line after line like this

testbench.v verilog.v

and pass it to iverilog.Further i wasn't able to get any test case with the usability of -s flag, though i tried to use it in followoing case but it gives no result and give wrong .vvp file which after executing produce no .vcd file.

module half_adder(
    output S,C,
input A,B
    );
xor(S,A,B);
and(C,A,B);

endmodule



module full_adder(
    output S,Cout,
    input A,B,Cin
    );
wire s1,c1,c2;
half_adder HA1(s1,c1,A,B);
half_adder HA2(S,c2,s1,Cin);
or OG1(Cout,c1,c2);

endmodule


module ripple_adder_4bit(
    output [3:0] Sum,
    output Cout,
    input [3:0] A,B,
    input Cin
    );
wire c1,c2,c3;
full_adder FA1(Sum[0],c1,A[0],B[0],Cin),
FA2(Sum[1],c2,A[1],B[1],c1),
FA3(Sum[2],c3,A[2],B[2],c2),
FA4(Sum[3],Cout,A[3],B[3],c3);

endmodule

i used -s option with half_adder and as well as with ripple_adder_4bit but in both cases it didn't worked out.Still figuring out their use.

For reference i had used this link