Electronic – the meaning of “do not populate test points” in a board schematic

One little nit: Only really sloppy developers use daily builds because one build a day means having to wait up to a day to find out if you broke the build.

The best solution is to build and test every single change individually before letting it hit the public branch and revert the change if it breaks the build in any way.

Doing any sort of automatic testing on a schematic or a board layout might be very hard or impossible, but everything you can automate should be automated via something like Hudson, things that come to mind are:

• ERC
• DRC
• BOM updating (check that the parts exist, are available and calculate total cost)
• Generate Gerbers and other manufacuring files.
• Generate PDFs of the schematic and PCB layers as well as 3d renderings of the PDB, BOM diff and other documentation.
• Drop a mail to the developer mailing list with the commit message and links to the output files, so developers can review the change easily.

The number of errors that can be caught automatically might not be terribly high, but having the CI system generate the output files means that it will happen correctly every time and that you don't forget some silly setting when doing it manually.

Neither the bypass capacitor C34 nor the SPI flash chip U3 has been populated on the board (since they're both inside the dashed box).

The footprints for both are there, and you could add them yourself (look for the designators C34 and U3). Be sure to add the bypass capacitor C34, if it's not already there, should you decide to add the flash chip.