I am trying to do some hspice simulation with some free 45nm CMOS transistor models. I found that an inverter can simulate properly with voltage as low as 0.25V, though it's slower.
My question is, in a controlled environment when speed is not a concern and the device is shielded, can such device run correctly at such low voltage?
Electronic – the lowest voltage a cmos transistor can operate
cmos
Related Solutions
CMOS (complementary metal oxide semiconductor) logic has number of desirable characteristics:
- High input impedance. The input signal is driving electrodes with a layer of insulation (the metal oxide) between them and what they are controlling. This gives them a small amount of capacitance, but virtually infinite resistance. The current in or out of a CMOS input held at one level is just leakage, usually 1 µA or less.
- The outputs actively drive both ways.
- The outputs are pretty much rail-to-rail.
- CMOS logic consumes very little power when held in a fixed state. The current consumption comes from switching as those capacitors are charged and discharged. Even then, it has good speed to power ratio compared to other logic types.
- CMOS gates are very simple. The basic gate is a inverter, which is only two transistors. This together with the low power consumption means it lends itself well to dense integration. Or conversely, you get a lot of logic for the size, cost, and power.
The short answer is - yes.
The slightly longer answer, it depends on the fabrication details of the transistor and it's targeted use case.
In all cases, below a critical length \$V_{TH}\$ decreases with decreasing length. However once this critical length is met the \$V_{TH}\$ can increase, stay the same or decrease. Here are some pictures.
image 1: flat
image 2: decreasing
image 3: increasing
There is also a correspondance between Gate Oxide thickness, the S/D structure design and this critical length.
Best Answer
Yes, as long as you are willing to make transistors with very low threshold voltages then the circuit will work. You can also adjust the thresholds dynamically using a back-gate bias.
However, the subthreshold leakage current will cause your logic to consume considerable dc power.