Electronic – the set in D FF

verilogvlsi

I'm trying to implement a 3-bit counter using basic gates (AND, OR, XOR, NOT etc..) around 3 D-type flip-flops. The input is an increment signal that when set to 1 will allow the counter to increment by 1. There are 3 outputs count(0), count(1) and count(2) where count(0) is the lsb.

But I'm not sure how can I handle the set in D-type flip-flops.
I have illustrate as follows but you can find there is set port in DFF.
So How can I make set in verilog? I'm not sure is this meaning reset? if yes, what if set is 1, is meaning negative reset? or positive reset?

How do I modify as above rule (the input is an increment signal that when set to 1 will allow the counter to increment by 1)? Am I interpreting it right or wrong?

UPDATE:

Is this the same thing?

always @ (posedge clk or negedge reset )  
if(set) 
    begin
      Q<=1'b1;  
    end

enter image description here

UPDATE:

   wire q0;                                      
   wire q1;
   wire q1_i = (q0 ^ q1);                        
   wire q2;
   wire q2_i = (q2 ^ (q0 & q1));


   dar u_dar1 ( ~q0 , clk , reset_n, q0);        
   dar u_dar2 ( q1_i , clk , reset_n, q1);       
   dar u_dar3 ( q2_i , clk , reset_n, q2);       

   wire [2:0] rere = {q2,q1,q0}; 

   module dar  (
                   data  , // Data Input
                   clk    , // Clock Input
                   reset , // Reset input 
                   q         // Q output
                   );
   input data, clk, reset ;
   output q;
   reg q;
   always @ ( posedge clk or negedge reset)
           if (~reset) begin
             q <= 1'b0;
             end  else begin
               q <= data;
               end

   endmodule

Best Answer

The Set-Reset-flip-flop is not often used, the syntax tends to look 'wrong' to those not used to seeing it. You can actually have 3 edge sensitive signals in the sensitivity list: Active low reset has priority.

always @(posedge clk or negedge reset or posedge set ) begin
  if (~reset) begin
    Q<=1'b0;  
  end
  else if (set) begin
    Q<=1'b1;  
  end
  else begin
    Q <= D;
  end
end

For a counter which will increment by 1 when enabled, there is no d=need for set_reset_flip-flops.

A clean RTL version could just be:

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
   Q <= 'b0;
  end
  else begin
    if (increment) begin
      Q <= Q + 1'b1;
    end
  end
end

Where increment is a synchronous signal. This has 3 flip-flops Q feeding into a Half adder with a single bit 1 as the other operand. You only need a half adder to increment by 1.

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