A D flip flop simply latches the value of a wire on it's D pin at the rising edge of a clock. Using three inputs (S, R, and Q (output of the DFF)), you need to create a small combinational circuit which mimics an SR flop:
- If
S is set, the value of D should be 1
- If
R is set, the value of D should be 0
- If neither is set, the value of
D should be Q
With these three statements it's simple to create a small truth table and from that to create the combinational circuit which should drive your D pin.
The inversion of input is because the NAND inputs are active (forcing the output) when low, and NOR inputs are active (forcing the output) when high. The current state is needed in the truth table as the next state may depend on both the current state and the inputs.
If you look at both outputs of an SR-latch, an active Set will override the output value of the gate Set is connected to. The same applies to reset, e.g. an active Reset will override the output value of the gate it is connected to. If you put both Set and Reset in the 'illegal' condition where both are active, you force both outputs to "00" for a NOR latch and to "11" for a NAND latch.
If both input signals start from the 'illegal' condition (both S and R active) you can create an arbiter circuit. When one of the inputs now goes inactive, the SR latch will remember which input was first to go inactive, for as long as the first input stays inactive. That can for instance be useful to arbitrate between multiple circuits utilizing a bus in an asynchronous design.
However for digital, sequential design the normal use of the SR-latch is to remember one of two previous and volatile states (not three as in the arbiter), thus you need to be careful about not setting both Set and Reset active at the same time, as then your final output will be determined by which of the inputs go inactive first. E.g. if both Set and Reset go inactive at the same clock edge, you have very little control over what state you end up in.
For nearly simultaneous transitions on both Set and Reset (for the SR transitions "10"=>"01", "01"=>"10", and "11"=>"00") you may enter a meta-stable state, where for a duration the output is neither '0' nor '1'. This pretty much means that you cannot determine how it will affect the gate(s) it is driving. Given enough time the metastable state will correct itself due to noise, but you don't know to which value. (In an arbiter you might not care about which way it goes, however you should design to keep a possible metastability event short&small enough to avoid producing an "acknowledge" that you end up retracting. This may not be possible unless you are doing a full custom design, and can be hard even then.).
Best Answer
I don't understand what you're trying to accomplish (try using shorter sentences), but one glaring problem in your design is the fact that you have the J and clock inputs of your FF tied together. This means that the J input will be changing at the same time as the clock edge, which almost certainly violates the setup and/or hold time requirements of the FF. Why don't you just tie the J input high?