Electronic – Using Buffer Ports in VHDL

vhdl

Is it bad coding practice to use Buffer Ports in VHDL?

I define an entity with an out port with o_done.

entity blahblah is
  port (
...other signals...
 o_done    : out std_logic;              
  );
end entity blahblah;

The synthesizer does not like me reading an out port and wont synthesize it – even though it is legal VHDL 2008 code. I can't change my synthesizer.

I use o_done in 2 clocked processes:

process begin
    wait until rising_edge(clk);
    if (reset = '1') then
      o_done <= '0';
    else
      if ( State1 ) then
        o_done <= '1';
      elsif ( o_done = '1' AND State0 ) then
        o_done <= '1';
      else
        o_done <= '0';
      end if;
    end if;
  end process;

  process begin
    wait until rising_edge(clk);
    if (reset = '1') then
      count <= to_unsigned(0, 8);
    else
      if( stateS0 AND done = '1' ) then
        count <= to_unsigned(0, 8);
      elsif( stateS1 AND y_counter >= 2 AND p >= 0 ) then
        count <= count + 1;
      end if;
    end if;
  end process;

Again, o_done, since defined as out in the port declaration, is not synthesizable since the synthesis engine isn't fully VHDL 2008 compatible. I can't change the synthesizer.

So how do I work around o_done being an output port and wanting to read it ?

Can I make an intermediate signal – how do I do this typically ?

Best Answer

Yea, you can use the simple solution of creating an internal signal:

signal done : std_logic ;

Use this signal inside your clocked process.

And simply assign it to o_done as a concurrent statement inside architecture definition:

o_done <= done ;

I haven't really had the need to use buffer ports in VHDL codes till now. This is something I extracted from Xilinx Vivado Synthesis Guide:

VHDL allows buffer port mode when a signal is used both internally, and as an output port when there is only one internal driver. Buffer ports are a potential source of errors during synthesis, and complicate validation of post-synthesis results through simulation. reference: Chapter 5, Xilinx Vivado Synthesis Guide

Related Solutions

Electronic – VHDL – passing through INOUT ports

Inouts can exist internally or externally. Indeed in reality they don't exist as physical gates, in both cases they are two gates in oposite directions in parallel.

Internally inout is usually imlememnted as an array of OR gates for the driver and multipel connections to AND gates for the receivers. There is no tristate internally.

Externally inout is usually two gates, the output one being able to be tristated by some common select signal.

VHDL does not care about 'internal' or 'external' signals.

So long as the VHDL syntax inferrs some means of deciding which device is being selected for access to the inout, the same code can be used as a top level or lower level module.
e.g. Within your module(s)

bus<=myoutdata when RD='1' else (others=>'Z');
myindata<=bus;

The else others bit suggests to VHDL that the bus is shared if bus is an inout. The shard signal, a version of which must go to every module that has access to the bus arbitrates who has access.

Electronic – Why is the simple counter VHDL not working? Where did the signals go

the rising_edge() parameter is only really for clock signals. One option would be the following:

clk_proc: process( clk, switch1, switch0 )
begin
    if switch1 = '1' then
        counter <= ( others => '0' );
    elseif rising_edge( clk ) then
        if switch0 = '1' then
            counter <= counter + 1;
        end if;
    end if;
end process;

This is known as an asynchronously reset process, which means that it'll reset the counter whenever reset (switch1) is high, regardless of clock state. A synchronously reset process would look the same as your second example:

clk_proc: process( clk, switch1, switch0 )
begin
    if rising_edge( clk ) then
        if switch1 = '1' then
            counter <= ( others => '0' );
        elsif switch0 = '1' then
            counter <= counter + 1;
        end if;
    end if;
end process;

You did state though that your second example didn't work as expected. My suspicion is that this is because the signals driving it are switches rather than clocked logic signals. Switches don't actually switch instantaneously, instead bouncing between on and off a few times before settling. You need to implement some sort of debounce process to produce a signal which is synchronous with your clock and can control your timer.

It's also worth mentioning that FPGA design is a lot easier if you simulate stuff first. Xilinx ISE includes a simulator - create a testbench and use it! That lets you easily see what's happening in your implementation before you ever get near hardware.

Best Answer

Related Solutions

Electronic – VHDL – passing through INOUT ports

Electronic – Why is the simple counter VHDL not working? Where did the signals go

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