Electronic – VHDL ieee.numeric_std: Division by zero defined

vhdl

As the title says, I'd like to know if the behavior of a zero division in ieee.numeric_std is somehow defined. If one does

signal a, b : unsigned (width1_g-1 downto 0);
signal c    : unsigned (width2_g-1 downto 0);

div_proc : process (clk_i)
begin
    if rising_edge(clk_i) then
        c <= a / b;
    end if;
end process;

for example, what will be the outcome of c?

Best Answer

In your example a and b are not initialized, but I assume you want a division with b := 0 somewhere, this answer is for FPGAs only:

From the numeric_std.vhd package:

-- NOTE: If second argument is zero for "/" operator, a severity level -- of ERROR is issued.
 -- Id: A.21   function "/" (L,R: UNSIGNED ) return UNSIGNED;

So in simulation this should crash. If it doesn't crash, you should find a better simulator.

In synthesis:

Vivado only supports division by powers of 2 in older versions and will try to infer a Divider LogiCORE unit for others, which doesn't support division by a constant 0 (so that's a synthesis error) and allows for optional error detection when trying to divide by a variable that might be 0. I haven't tried what happens if you turn this inference off in current editions, but I'd suspect it again only accepts powers of 2.
Current Quartus products try to infer a DSP divisor with extremely similar limitations as the Xilinx Divider. No idea what happens when you try to synthesize it in pure LUTs. I know division can be infered for non-binary powers and it's horrible.

Don't try to divide by zero.

Related Solutions

Electronic – Why is the simple counter VHDL not working? Where did the signals go

the rising_edge() parameter is only really for clock signals. One option would be the following:

clk_proc: process( clk, switch1, switch0 )
begin
    if switch1 = '1' then
        counter <= ( others => '0' );
    elseif rising_edge( clk ) then
        if switch0 = '1' then
            counter <= counter + 1;
        end if;
    end if;
end process;

This is known as an asynchronously reset process, which means that it'll reset the counter whenever reset (switch1) is high, regardless of clock state. A synchronously reset process would look the same as your second example:

clk_proc: process( clk, switch1, switch0 )
begin
    if rising_edge( clk ) then
        if switch1 = '1' then
            counter <= ( others => '0' );
        elsif switch0 = '1' then
            counter <= counter + 1;
        end if;
    end if;
end process;

You did state though that your second example didn't work as expected. My suspicion is that this is because the signals driving it are switches rather than clocked logic signals. Switches don't actually switch instantaneously, instead bouncing between on and off a few times before settling. You need to implement some sort of debounce process to produce a signal which is synchronous with your clock and can control your timer.

It's also worth mentioning that FPGA design is a lot easier if you simulate stuff first. Xilinx ISE includes a simulator - create a testbench and use it! That lets you easily see what's happening in your implementation before you ever get near hardware.

Electronic – VHDL how to make a process with sensitivity list wait

For much testbench code, we do not use looping processes and process sensitivity lists to search for things. Instead, we use wait to find events.

TestProc : process 
begin
  Out1 <= '1' ; -- Steady 1 after this point.

  -- Find Reset as it deactivates
  -- a better alternative than waiting for an ad-hoc amount of time
  if Reset /= ACTIVE then
    wait until Reset = ACTIVE ; 
  end if; 
  wait until Reset /= ACTIVE ; 

  -- find ready at a level 1
  if ready /= '1' then 
    wait until ready = '1' ; 
  end if ; 
  Out2 <= '1' after 5 ns ; 

  -- find a rising edge of Clock
  -- Assumes that clock always transitions from 0 to 1 
  wait until Clk = '1' ; 
  Out2 <= '0' after 5 ns ; 
  ...

  -- Also find a rising edge of Clock
  -- rising_edge is extra work for the simulator and probably not necessary here
  wait until rising_edge(Clk) ; 
  Out2 <= '1' after 5 ns ; 
  ...

  std.env.stop ; -- stop the testbench
end process TestProc ;

If you are looking for a behavioral model that drives Out1 to a static value, but inverts Out2 5 ns after each time Ready rises to a 1, then you can do the following:

signal Out2 : std_logic := '0' ; 
. . . 
FollowReady : process  
begin 
  -- initialization 
  Out1 <= '1' ; 
  wait for 20 ns ; 

  -- looping process like behavior
  loop 
    -- Ready is a design signal.  Only detect a 0 to 1 change
    wait until rising_edge(Ready) ;
    Out2 <= not Out2 after 5 ns ; 
  end loop ; 
end process ;

Best Answer

Related Solutions

Electronic – Why is the simple counter VHDL not working? Where did the signals go

Electronic – VHDL how to make a process with sensitivity list wait

Related Topic