Electronic – VHDL Unconstrained port in a entity

genericvhdl

I've a problem with the definition of an entity. I'm writing a wrapper that accepts several generic. Among these generic there are some boolean values that have the function to enable or disable the transmission of some input signal to the output of the entity. I'd like to have the width of the output signal related to the boolean values. This is what I want to do :

entity of DUT is 
   generic( 
     DATA_1_WIDTH : natural := 16;
     DATA_2_WIDTH : natural := 16;
     SWITCH_1 : boolean := FALSE;
     SWITCH_2 : boolean := FALSE;
     ....
     );
   port (
     clk : in std_logic;
     rst : in std_logic;
     DATA_1 : in std_logic_vector(DATA_1_WIDTH - 1 downto 0);
     DATA_2 : in std_logic_vector(DATA_2_WIDTH - 1 downto 0);
     ....
     DATA_OUT : out std_logic_vector);

Where the width of "DATA_OUT" change with the values of the switches :

When SWITCH_1 = TRUE and SWITCH_2 = TRUE => width of DATA_OUT = DATA_1_WIDTH + DATA_2_WIDTH + constant;
When SWITCH_1 = TRUE and SWITCH_2 = FALSE => width of DATA_OUT = DATA_1_WIDTH + constant;

And so on.

Can someone tell me a way to do this ?

Best Answer

Depending on how the rest of your entity works, you may be able to leave DATA_OUT as an unconstrained array. This means that you don't give it a width in the port map, and that it takes the width of the signal that you connect to it in the instantiating entity. This basically passes the problem up one level in the hierarchy.

You can also achieve this using a function. Create a package for your design, and within this create a function, something like this:

function GetDataOutWidth(Switch1, Switch2 : boolean; Data1Width, Data2Width : integer) return integer is
  constant WidthConstant : integer := 2; -- Or whatever
begin
  if (Switch2) then
    return Data1Width + Data2Width + WidthConstant;
  else
    return Data1Width + WidthConstant;
  end if;
end function;

Your code can then use this function in the port map, something like this:

DATA_OUT : out std_logic_vector(GetDataOutWidth(SWITCH_1, SWITCH_2, DATA_1_WIDTH, DATA_2_WIDTH)-1 downto 0)

Related Solutions

Electronic – VHDL: Component vs Entity

Here's an analogy which helps some people (especially those from a physical electronics background):

A component tells the compiler "there's going to be something with these sorts of pins on it called this at some point, but don't worry for now". It sort of defines a "socket". You can go on to describe what "wires up" to that "socket" etc.

An entity is something specific with a name and a set of pins, which the compiler can then "plug in" to that "socket" (and hence be connected to the "wires").

Note that you don't need a component you can do "direct instantiation" which means the compiler already knows about an entity so the "socket" doesn't need to be defined separately. In fact, that would be my recommended approach, as otherwise the component is an extra level to be kept in sync.

You need to use components if you are mixing Verilog and VHDL and need to use a Verilog block within the VHDL. Then the component is the socket and not until much later on can the compiler/elaborator plug the Verilog into the socket.

Electronic – Wrong outputs in VHDL entity

The first thing I see, which isn't likely causing your problem, is a lack of any kind of reset. ModelSim does not automatically declare all signals to be '0', and trying to say s <= not s when s is not 1 or 0 is not going to give you what you want. I see you declaring them all '0' at the top but a proper circuit would have a reset input that you briefly drive at the start of your simulation.

Your basic counter process looks wrong; basically when the count reaches ten you're outputting a '1' and for the other 9/10ths of the time you're outputting a '0' (for the 100k example, the 1Hz example would be a 1us pulse high and a 999us low time. I think what you want is something like this:

gen_clk100: process(clk, rst)
begin
    if rising_edge(clk) then
        if count = 10 then
            clk100 <= not clk100;
            count <= 0;
        else
            count <= count + 1;
        end if;
    end if;

    if rst = '1' then
        clk100 <= '0';
        count <= 0;
    end if;
end process;

Note several things:

I'm not incrementing all the time. I increment if the count is not at its max, and increment otherwise.
I'm toggling the output clock when the maximum count is reached
I've included an asynchronous reset (with synchronous clear) -- this ensures that your signals initialize correctly and have no metastability problems when reset is released.

You also mention that the other sections are the same. I think you're having a problem with multiple drivers like Yann mentioned. Check and double-check your code to make sure you are not assigning the output in two different processes, because that is exactly what the simulation is saying you're doing. Better to either make a generic counter module or...

Why so many counters? All your frequency dividers can be handled with a single count and then "peeling off" the conditions to do the divisions you're interested in. You could also have a single counter and use the mod (modulus) operator to handle each divider case.

Finally, I'd also use real or integer types for the count instead of std_logic_vectors but that's just me.

Best Answer

Related Solutions

Electronic – VHDL: Component vs Entity

Electronic – Wrong outputs in VHDL entity

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