The package contains the following lines:
file INPUT: TEXT is in “STD_INPUT”;
file OUTPUT: TEXT is out “STD_OUTPUT”;
For some reason these remind me of the standard input and output streams from my C language lessons. What do these mean here? Is it really possible to read/write the standard input/output stream by using this package? How?
Best Answer
Short answer: Yes :)
Unfortunately not every simulator supports it.
Currently, I know only GHDL and ModelSim / QuestaSim. I have no info on iSim or xSim.
I don't know any synthesis tool which supports STD_IN and STD_OUT. Xilinx XST has file I/O support but I think no support for STD_IN/STD_OUT.
Vivado has no file I/O support and Quartus does not support std.textio.