To get straight to the question asked, you can find the logic levels for 10H or 100H logic by going to any datasheet for a part in those families. On Semi is the main vendor for those parts (though Fairchild and other vendors have second-sourced them as well), and you can get a list of all the parts in the family here.
One thing to be aware of is that ECL logic levels are referenced to VCC rather than VEE, so the logic level will be something like Vih ~= Vcc-1 and Vil ~= Vcc - 1.7. For the full range of mins and maxes for the input and output levels, check an actual datasheet.
A previous answer stated that ECL logic is "a differential logic standard." While most ECL parts use differential inputs and outputs, many complex functions, especially in the earlier generations, were built with single-ended i/o's.
It was also stated that ECL runs "much faster than TTL, and draws more power". While its typically true that ECL will draw more power for a gate that doesn't switch often, the power draw of ECL doesn't increase as much as TTL when the switching frequency goes up. So there's typically some frequency above which ECL will actually draw less power than the same function in TTL.
Another issue to watch out for is that MECL parts date from the era when engineers designed from paper data books, rather than downloading data sheets part-by-part off the net. Some of the characteristics of these parts were only described in the introductory chapters of the databook, and not in the individual parts' datasheets. (For example, the pin-outs for certain packages were not in each datasheet, but a translation table from DIP pins to pin #'s for other packages was included in the introduction.) I think that most of this information can nowadays be found in the App Note "General Information for
MECL 10H and MECL 10K".
There was once upon a time an excellent "Design Handbook" for using the MECL parts that had lots of information on controlled impedance design, differential logic design, etc., that is still relevant today...sadly I can't seem to find this handbook online at the moment.
Its a term used to try to bridge the world from ASIC & discrete logic to how FPGA function with their slices and lookup tables.
One slice could be used to create a single AND gate or a to some extent part of a larger adder. By rationalising the equivalent logical gates required is some pseudo way of marketing their size.
Best Answer
http://quartushelp.altera.com/10.0/mergedProjects/reference/glossary/def_alm.htm
LE has meant "logic element" for many years, although what defines a logic element is not entirely static, in Altera-land is usually means a 4-input look-up table (sometimes called a 4-LUT) + a d-type flipflop (DFF).