Would any of the via's in the picture be considered a via-in-pad?
or is it only if it's dead center of the pad?
Via-in-Pad – Definition and Applications
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That's a new one on me! There are other reasons for putting a via in the pad, but strengthening a connector is a new one.
The weakest part of an SMD pad is that the copper could delaminate from the fiberglass, and lift off the PCB itself. Anything you could do to prevent that would help, including making the pad larger or putting a via in the pad itself.
But you have to be careful, since putting a via in the pad can cause other issues. The first problem is that it might make the pads not flat enough, so a connector pin won't make good contact with the pad and thus not get soldered well. The second issue is that the solder could get wicked down the via and leave nothing left for the connector pin. This isn't a big issue if you are hand soldering, but can be a problem when doing it with automation.
Honestly, if connector strength is an issue then seriously consider going to a through-hole connector or some type of connector that gets strength from some other means. Maybe a connector that gets bolted to the chassis itself (and stress on the PCB is minimal). Or even a different connector entirely.
Vias will not impact the assembly of the PCB provided that their effect is carefully considered in the assembly process.
Many RF ICs and SMD power MOS devices require solid thermal connections to internal planes in order to wick away generated heat and endure a low impedance GND path. Vias are known to wick up solder paste during the reflow process and there are several options to mitigate this. The correct combination of via count, via size and solder paste mask will ensure a very repeatable assembly process.
The screen capture above is of a GPIO expander with 16 non-plugged vias which are tented only on the bottom side. It is a 6 layer board with solid 1oz ground planing on all layers. Paste mask is revealed in grey. Most IC manufacturers will specify the solder paste and via requirements, otherwise it may be extracted from IPC-7351-2004 Generic Requirements for Surface Mount Design and Land patterns. There are also many free and open source land pattern generators online.
Best Answer
I would think about it this way, why would you care if a via was "via in pad"? Because you want to treat it a special way, and perhaps because that treatment will cost you more at fabrication. So why treat a via that's in a pad any different? For me with a through hole via in pad I'm worried about solder wicking through the barrel of the via and possibly to the back of the board. Either way it's the ultimate mechanical, electrical, and possibly thermal connectivity of my joint that I'm worried about.
To fix that we usually fill the vias with either conductive or non-conductive fill and then plate them flat (I've been using non-conductive lately because it saves a step).
Now to your question, when would I treat a via specially and call it via in pad in these cases? I would say it's anytime I think solder might flow into that hole. So perhaps even your first example if there is not enough clearance for solder mask between the hole and the pad so that no solder will flow in the worst case. Even your second case might warrant it if there's not enough room for solder mask, that's something I would expect to get flagged at DFM.
On an interesting side note at our fabs once you do one via in pad it costs no more for us to do everything via in pad. So if you find yourself having to make that decision for one case maybe you can do it everywhere.