Electronic – What does delta stands for in ModelSIM

modelsimsimulationvhdl

I ran a simulation for a combinational logic circuit with 8 inputs, 4 outputs inside MODELSIM. When I view the simulated waveform everything looks fine, however when I export result to a list file there are some intermediate valued related to deltas inside a time slot like this:

t(ns) delta               output input
    460  +1                   4'h1 8'h2E 
    460  +4                   4'h0 8'h2E 
    460  +5                   4'h2 8'h2E 
    470  +1                   4'h2 8'h2F 
    470  +4                   4'h3 8'h2F 
    480  +1                   4'h3 8'h30 
    480  +4                   4'h2 8'h30 
    480  +5                   4'h4 8'h30 
    480  +6                   4'h6 8'h30 
    490  +1                   4'h6 8'h31 
    500  +1                   4'h6 8'h32 
    500  +4                   4'h7 8'h32 
    500  +5                   4'h5 8'h32 
    510  +1                   4'h5 8'h33 
    510  +6                   4'h7 8'h33 
    510  +9                   4'h5 8'h33

I want to know what are these intermediate values and will they cause problem for my circuit or not?
e.g. there are 3 value for t=460ns

Best Answer

Simulation cycles are characterized by those that result in the advancement of simulation time and those that don't. Those that don't are known as delta cycles.

From a simulation cycle resulting from the advancement of simulation time assignment to a signal without a delay (e.g. after, wait for) will cause a delta cycle as the next simulation cycle without changing the current simulation time. Delta cycles occur until there are no more signal assignments to the current simulation time.

It's how the simulator emulates parallelism. Simulation consists of executing processes in response to events on signals causing processes to wake from sleep. And every concurrent statement is devolved into equivalent processes and/or block statements which represent hierarchy, function calls are expressions.

When there are no events scheduled at the current simulation time, simulation time is advanced to the earliest any event is scheduled in any projected output waveform for any driver (there's a queue).

When there are no scheduled events at a future simulation time, simulation time is advanced to the maximum simulation time and simulation is complete.

This isn't specific to Modelsim, the simulation cycle is defined in the VHDL LRM, and is used for simulating most HDLs. It was originally defined in CONLAN an HDL project that went from 1971 to 1983.

The number of delta cycles executed can be used as feedback to the efficiency of a design model, you can set the maximum number allowed in a simulation.

The information can also be used to construct a graph or waveform showing sequence of model execution across all simulation cycles.

The information is of no particular interest unless you want to understand sequence of assignments in model execution or improve model performance.

If you trace back how the values are generated for those +4, +5 and +9 delta cycle occurrences you'd learn why there are so many.

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