Electrical – Why does modelsim show St0, St1 & Pu0 for value of logic signal

It has to do with what can be easily evaluated at elaboration time, formally, what is called a "locally static expression". This is an obscure looking rule, but it deserves some thought - eventually it does make some sense, and your simulator is quite correct in alerting you by generating non-obvious results.

Now, temp(1) can be evaluated at compile time (even earlier than elaboration time) and it can generate a driver on bit 1 of "temp".

However, temp(i) involves a bit more work for the tools. Given the trivial nature of the loop bounds here ( 1 to 4 ) it is obvious to us humans that temp(0) cannot be driven and what you are doing is safe. But imagine the bounds were functions lower(foo) to upper(bar) in a package declared somewhere else... now the most you can say with certainty is that temp is driven - so the "locally static" expression is temp.

And that means that the process is constrained by these rules to drive all of temp, at which point you have multiple drivers on temp(0) - the process driving (no initial value, i.e. 'u') and the external temp(0) <= '0';. So naturally the two drivers resolve to 'U'.

The alternative would be a "hacky little rule" (opinion) that if the loop bounds were constants, do one thing, but if they were declared as something else, do something else, and so on ... the more such oddball little rules there are, the more complex the language becomes... in my opinion, not a better solution.

This is definitely a Quartus II issue. I'd suggest you you delete state from the simulation display and re-add it insuring it matches Figure 29 on Page 29 of the tutorial you provided the link for, above.

I wrote a test bench that reproduces the waveform from the book. You can use it to insure the arbiter works as intended even if you can't display state:

library ieee;
use ieee.std_logic_1164.all;

entity arbiter_tb is
end entity;

architecture foo of arbiter_tb is
    signal clk:        std_logic := '0';
    signal reset:      std_logic := '0';
    signal r:          std_logic_vector(1 to 3) := (others => '0');
    signal g:          std_logic_vector(1 to 3);
begin
CLOCK:
    process 
    begin
        wait for 50 ns;
        clk <= not clk;
        if Now > 1150 ns then
            wait;
        end if;
    end process;

DUT:
    entity work.arbiter
        port map (
            clk => clk,
            reset => reset,
            r => r,
            g => g
        );

STIMULUS:
    process
    begin
        wait for 51 ns; 
        reset <= '1';
        r <= (others => '1');
        wait until rising_edge(clk) and g(1) = '1';
        r(1) <= '0';
        wait until rising_edge(clk) and g(2) = '1';
        r(2) <= '0';
        wait until rising_edge(clk) and g(3) = '1';
        r(3) <= '0';
        wait;
    end process;

end architecture;

And this is as close as I could get with ghdl and gtkwave:

If re-adding state didn't work you'll need to find Altera specific help.