Electronic – When does Direct Source-Drain tunneling become a problem

There's no guarantee with your device.. it's 300nA at 25C and 3.3uA at high temperature typical. In fact, if the distribution of leakage is Gaussian (a rather big "if"), you'd expect 1uA would be a reasonable guess for the maximum (\$3 \sigma\$).

If you want low typical leakage, you should pick a device that's no bigger (in terms of drain current rating) than you need, and one with a relatively high \$V_{TH}\$ rather than a ginormous MOSFET rated for 1.8V drive. Some small signal MOSFETs are typically 1pA at 25°C, which is 300,000 times better than the SM74611.

Most people don't care about leakage that much, so the maximum figures tend to be conservative. I don't know any alternative to looking at data sheets to see what is guaranteed or specified as typical. You can always measure it yourself, but the next batch could (in theory anyway) be wildly different. The same part number from a different manufacturer probably will be different.

When you apply a voltage to the gate of an NMOS FET that is greater than the threshold voltage \$V_{t}\$, a channel of electrons is formed under the gate. That channel connects the drain and source so that when you apply a voltage \$ V_{ds}\$, a current flows from between these terminals. In this mode, the MOSFET behaves almost like a resistor, so the current flow depends (although not linearly) on \$V_{ds}\$, but the current will also increase with the gate-source voltage \$V_{gs}\$ because increasing this makes the channel deeper, reducing its resistance. That explains the first part of the curve (active or triode).

However, the electric field near the drain depends not just on \$V_{gs}\$ but also on \$V_{ds}\$. Once \$V_{ds} = V_{gs} - V_{t}\$ (called \$V_{ds,sat}\$) the electric field is cancelled near drain and the channel becomes shorter, no longer reaching the drain, leaving a depletion region between the end of the channel and the drain. Any further increase in \$V_{ds}\$ is dropped across this depletion region so the voltage across the channel stays constant at \$V_{ds,sat}\$ and the current flow is also constant. That is the second region of the curve (saturation).

The explanation of the saturation region above would suggest that FET current is constant with \$V_{ds}\$ in the saturation region. Obviously, from the current-voltage curves we can see that this is not the case, and actually the current slowly rises. This is due to an effect called channel length modulation. As \$V_{ds}\$ continues to increase, it cancels the inverted channel even further from the drain, leading to the channel shortening. This reduces the channel resistance (resistance is proportional to length) leading to higher current flow.

There are obviously a lot of second order effects not covered here, but those are the basics!