bufferdigital-logic
Why does the use of a Tristate-Buffer in digital-circuits prevent exceeding the fan-out of logic gates? The number of Logic Gates-inputs, that are connected to a single output is the same, as using no tristate-buffer.
For example: a logic that doesn't work, due to the high fan-out
and the same logic gate with an Buffer, so it works.
To expand a bit on @Barsmonster's answer, if you look at the CMOS implementation of a gate, there is a "pull-up" network of P-type transistors and a "pull-down" network of N-type transistors. The inverter is the simplest case of such a gate and it looks something like this:
When A (labeled "1" in your diagram) is set to Vss (GND), the P-type transistor turns on (and the N-type transistor turns off), and Q (labeled "2" in your diagram) is effectively connected to Vdd. When A is set to Vdd the N-type transistor turns on (and the P-type transistor turns off), and Q is effectively connected to Vss.
The current limit they are talking about is how much the N-type transistor can sink without burning up.
A tristate buffer has a certain minimum time from when the enable is asserted to when its output impedance starts to fall (the drivers start to turn on). Also, it has a certain maximum time from when the enable is negated to when the drivers are fully off (high output impedance).
If the former is not greater than the latter, then you cannot use the same (well, inverted) enable signals directly for two buffers on the same bus; you need to guarantee the timing by other means — either by using different clock edges, or perhaps by using a delay line.
Best Answer
It's not the fact that it's tri-state that makes the difference, it's the fact that it's a buffer. Buffers are generally designed to supply more current than a normal logic stage.
They still have a fanout limit; it's just a higher limit. What that limit is, you will have to learn from the datasheets for your logic family and your buffer.
A 74LS00 input can consume 20 uA pulled high, or 0.4ma pulled low. The 74LS00 gate can source 400 uA and sink 8 ma, 20x as much as the input current, so its fanout is 20.
But the 74LS240 driver can source 15ma and sink 24ma, so it can pull 60 TTL inputs low, and its fanout is therefore 60.
If one buffer isn't enough you can connect 2 or more in parallel (up to the normal fanout for your logic stage) each driving a different set of gates.
You might well ask why it can source 15ma instead of just 60 * 20ua = 1.2ma. That's because buffers also have to drive relatively long wires with high capacitance, and doing so at any speed takes current in both directions (pulling both high and low). If you need 15ma to drive the cable fast enough, you would also have to reduce the fanout (number of inputs it can pull low) or live with slightly lower speed.
You might also ask why I'm using a logic family about as old as Abba : that's because modern CMOS logic requires so little input current that any fanout number is likely to be in the thousands; other issues like the wire speed problem matter much more.
Fanout is still there in the background and shouldn't be totally forgotten, but any logic course that gives it much attention probably needs updating!