Digital Logic – Why is the Output Inverted in an IC 74154 Used as a Demux?

Just add a second NPN as an inverter.

^{simulate this circuit – Schematic created using CircuitLab}

Adjust resistor values and add speed-up caps and/or Schottky clamps to meet your speed and current requirements.

I think it's a poor problem to begin with, because it's not very clear what the overall purpose is and is generally not uniquely solvable as BlueSky has pointed out.

$$\begin{array}{ccc|ccc|ccl} a & b & c & e & c & d & H & & \\ \hline\hline 0 & 0 & 0 & & 0 & 0 & 0 & & \\ 0 & 0 & 0 & & 0 & 1 & 0 & & \\ 0 & 0 & 1 & & 1 & 0 & 0 & & ⬅ \\ 0 & 0 & 1 & & 1 & 1 & 1 & & \\ 0 & 1 & 0 & & 0 & 0 & 0 & & \\ 0 & 1 & 0 & & 0 & 1 & 0 & & \\ 0 & 1 & 1 & & 1 & 0 & 1 & & \\ 0 & 1 & 1 & & 1 & 1 & 1 & & \\ 1 & 0 & 0 & & 0 & 0 & 0 & & \\ 1 & 0 & 0 & & 0 & 1 & 1 & & ⬅ \\ 1 & 0 & 1 & & 1 & 0 & 1 & & \\ 1 & 0 & 1 & & 1 & 1 & 1 & & \\ 1 & 1 & 0 & & 0 & 0 & 0 & & \\ 1 & 1 & 0 & & 0 & 1 & 0 & & \\ 1 & 1 & 1 & & 1 & 0 & 1 & & \\ 1 & 1 & 1 & & 1 & 1 & 1 & & \\ \end{array}$$

This is both truth tables side by side, i.e. left-hand side $$e = G(a,b,c)$$ and right-hand side $$H = F(e,c,d)$$

Now, it's immediately obvious that F couldn't be a simple gate, i.e. not a 3-input and, or, nand, nor, xor, not xor (biconditional), because some lines where H = 1 contain zeros, e.g. line 7.

Now, looking at the table some more, most of the time, H = F(e,c,d) = c. In fact, only two lines don't show this behavior, which I marked with ⬅.

Now, the marked lines appear only once with not c and every where else they're c. This means the difference must be in the e input to F in those lines, i.e. e must be 1 for both groups of lines and 0 for all others or vice versa. The choice of which lines have e = 1 and which have e = 0 is arbitrary, hence the solution to this problem is not unique. Notice that groups of two lines share the same e, because the inputs to e = G(a,b,c) are the same.

$$\begin{array}{ccc|ccc|ccl} a & b & c & e & c & d & H & & \\ \hline\hline 0 & 0 & 0 & 0 & 0 & 0 & 0 & & \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 & & \\ 0 & 0 & 1 & 1 & 1 & 0 & 0 & & ⬅ \\ 0 & 0 & 1 & 1 & 1 & 1 & 1 & & \\ 0 & 1 & 0 & 0 & 0 & 0 & 0 & & \\ 0 & 1 & 0 & 0 & 0 & 1 & 0 & & \\ 0 & 1 & 1 & 0 & 1 & 0 & 1 & & \\ 0 & 1 & 1 & 0 & 1 & 1 & 1 & & \\ 1 & 0 & 0 & 1 & 0 & 0 & 0 & & \\ 1 & 0 & 0 & 1 & 0 & 1 & 1 & & ⬅ \\ 1 & 0 & 1 & 0 & 1 & 0 & 1 & & \\ 1 & 0 & 1 & 0 & 1 & 1 & 1 & & \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 & & \\ 1 & 1 & 0 & 0 & 0 & 1 & 0 & & \\ 1 & 1 & 1 & 0 & 1 & 0 & 1 & & \\ 1 & 1 & 1 & 0 & 1 & 1 & 1 & & \\ \end{array}$$

Thus, we have tagged the "special" lines with e = 1 and all "regular" lines with e = 0, thus

$$\text{Regular lines:}\quad\quad \overline{e}c \quad\quad \text{Our observation that for most lines $H = c$}$$ $$\text{Line 4:}\quad\quad ecd \quad\quad \text{First tagged group, second line.}$$ $$\text{Line 10:}\quad\quad e\overline{c}d \quad\quad \text{Second tagged group, first line.}$$

Therefore, we can write F as $$ F(e,c,d) = \bar{e}c \vee ecd \vee e\bar{c}d$$ With the truth table for F (right hand side of table) done, we can read G as $$G(a,b,c) = \overline{a} \overline{b}c \vee a\overline{b} \overline{c}$$

Problem solved. I reiterate that I think it's a poor question/problem, because both gates are in fact not "obvious" simple logic gates. Still, I hope you could take away something from my solution to this problem.