Electronic – Why would this logic gate use negative voltages

bufferdigital-logicpower supply

I'm reading a data sheet for a hex buffer with enable- a pretty simple logic DIP. Here's the logic diagram and pin assignment:
Hex buffer diagram

This all makes sense to me until I look at the electrical parameters. VCC=0V? VEE=-5.2V? It seems to me that this part could be used with VEE=0V and VCC=5.2V with no issues- after all, it's just an issue of potentials, right? But if that's the case, why would anyone ever specify parameters like this? I feel like I must be missing something.

Edit: OK, I was missing something big an obvious. I get that it's ECL. But- could I still use it like normal, with VEE=0V and VCC=5.2V?

Crazy parameters

Best Answer

ECL outputs are referenced to the most positive supply rail. This means that any noise appearing on the most positive supply rail will be directly coupled onto the output signal. For example, if the power supply is 5V and GND, then all outputs would be referenced to 5V, and any noise on the 5V supply would also be seen at the ECL outputs. Therefore, the older literature calls for ECL chips to be powered by a negative power supply, such as -5V and GND. By using GND as the most positive supply rail, it is easier to maintain cleaner signals at the ECL outputs. GND is generally found to be less noisy as compared to a non-GND potential. This does not mean it is impossible to use a positive power supply. It does mean that precautions must be taken to ensure very little noise is coupled onto the most positive supply rail in order to maintain clean outputs

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