Finite State Machine for Synchronous Circuit

digital-logicstate-machines

Using the diagram below I have to fill out the state table for Q1+, Q0+, G, and F.

Assuming Q0+ and Q1+ are the inputs to the left and right flip-flops, respectively, fill out the following state table for the circuit above:

Q1: 0 0 1 1

Q0: 0 1 0 1

Q1+: 0 1 0 1

Q0+: 1 0 1 0

G: 0 0 1 1

F: 0 1 0 1

Based on the diagram and the values of Q1 and Q0, would my values be correct for Q1+, Q0+, G, and F? Thank you!

Best Answer

Assuming:

  • Q0 is the output of the DFF on the left,
  • Q1 is the output of the DFF on the right,
  • Q0+ = Q0* = Q0 next,
  • Q1+ = Q1* = Q1 next

We can derive expressions for the values Q0*, Q1*, F and G from observations of the circuit.

  • F = Q0 (connected to output of Q0 DFF)
  • G = Q1 (connected to output of Q1 DFF)
  • Q1* = Q0 (connected to output of Q0 DFF)
  • Q0* = ~Q1 (connected to inverted output of Q1 DFF)

You may notice that all of the above equations only depend on the Q0 and Q1 state registers. This means this is a Moore FSM since the output depends only on the present state. We can build the entire truth table from just the Q0 and Q1 states on the left side:

Truth Table

Q1 Q0 | Q1* Q0* G F
-------------------
0  0  | 0   1   0 0
0  1  | 1   1   0 1
1  0  | 0   0   1 0
1  1  | 1   0   1 1