Don't think for one minute that just because you have an FPGA that learning about 74xx is obsolete.
For designing with FPGA you must be able to 'see' the logic working in your head at a discrete gate level (you will learn this skill from discrete logic chips 74xx, cmos 40xx ).
Programming an FPGA is NOT like writing a computer program, it looks like it is, but only the idiots will tell you it is.
you will see many ,many people on the net talk about their FPGA design is big or slow, in reality they just don't understand how to think at a true multiprocessing parallel gate level and end up serial processing most of what they try to do, this is because they just crack open the design tools and start programming like they are writing 'C' or 'C++'
- In the time it takes to compile a design for an FPGA on a home computer, you can breadboard a simple logic design in 74xx
- Using FPGA for a design you MUST work with simulators rather than with the 'hard' FPGA
That is to say, if your 74xx design is malfunctioning you can fiddle with the connections, with an FPGA you must re-write, re-run a simulation, and then spend upwards of 30 minutes re-compiling the FPGA design.
Stick with the 74xx or 40xx range, build some 'adders', 'shifters', and LED flashers with gating, once you are used to seeing discrete chips it becomes easier when working with a massive 'blob' that is an FPGA
You are almost done, all what's left is to get the logic equations from the table. Remember that w is an input so it is part of the present state and we will use it to compute values of the next state.
Let w be a 2 bit number, $$w = w_1w_0$$
so if we let A = 00, B = 01, and C = 11 then:
$$
w = \left.\begin{cases} \bar{w_1} \bar{w_0}
& w = A\\ \\ w_1 \bar{w_0} & w = B\\ \\
w_1 w_0 & w = C \end{cases} \right\} \\ \\
$$
and the 5 states are
$$
S_i = \left. \begin{cases}
\bar{y_2 }\bar{y_1 }\bar{y_0 }& i = 1 \\ \\
\bar{y_2 }\bar{y_1 } y_0 & i = 2 \\ \\
\bar{y_2 } y_1 \bar{y_0 } & i = 3 \\ \\
\bar{y_2 } y_1 y_0 & i = 4 \\ \\
y_2 \bar{y_1} \bar{y_0 } & i = 5
\end{cases} \right\}
$$
To get the logic for computing the next state you get the boolean equation for each bit of the next state separately.E.g to get the logic for computing y0 :
$$
y_{0 , next} = S_1 A + S_2 A + S_3A + S_3 C + S_4 A + S_5 A
$$
$$
y_{0, next} = \bar{y_2 }\bar{y_1 }\bar{y_0 } \bar{w_1} \bar{w_0}
+ \bar{y_2 }\bar{y_1 } y_0 \bar{w_1} \bar{w_0}
+ \bar{y_2 } y_1 \bar{y_0 } \bar{w_1} \bar{w_0}
+ \bar{y_2 } y_1 \bar{y_0 } w_1 w_0
+ \bar{y_2 } y_1 y_0 \bar{w_1} \bar{w_0}
+ y_2 \bar{y_1} \bar{y_0 } \bar{w_1} \bar{w_0}
$$
which reduces to
$$
y_{0, next} = \bar{w_1}\bar{w_0} + \bar{y_2 } y_1 \bar{y_0 } w_1 w_0
$$
Repeat this for y2 and y1, to get the rest of the combinational logic required.
The output(z) is high when this state machine is in state 5 so Z will be given by:
$$
z = S_5 = y_2 \bar{y_1} \bar{y_0 }
$$
This is a moore machine as Z is only dependent on the current state.
Best Answer
"State machine" is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.
Electronic state machines started out as analogs of the mechanical state machines (including such examples as adding machines) that preceded them.
Your list of questions is far to broad to address here in EE.SE. You really need to do some Internet research on your own and then come back with more specific, focused questions.