How does this reverse NOT gate work

aludigital-logiclogisimschematicsttl

I created a 74LS181 circuit in Logisim based on TI's datasheet. Notice how the NOT gate for the B0 input has a dot before the triangle:

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Here's a screenshot of my circuit:

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Notice that my inversion for the B0 – B3 inputs are just plain NOT gates as Logisim doesn't seem to offer a variation of it. I find the 74LS181 a bit confusing as it can handle both LOW inputs and HIGH to achieve different operations.

I've double checked the netlist, although its possible i've made mistakes. But the operation above is not right. F is supposed to = 1001 (decimal 9) as the function is: F = A MINUS 1. The input of A is 1010 (decimal 10). I am running in arithmetic mode as M = 0. The status flags S0 – S3 = 0 which is the circuits first function. Also the carry-in Cn is 0. The odd thing, is if Cn is 1, then the output is 1010 (10 decimal) which would be correct as it would equate to F = A MINUS 1 + 1.

I'm wondering if the NOT gate is affecting this, or if I have an error in my netlist.

Best Answer

Ahh, I figured it out. I had the F0 - F3 bits reversed in my head. 0110 is correct as the input is 0101 (decimal 5) not 1010 (decimal 10). This results in the output 0110 (decimal 6) as F = A PLUS 1.