counterdigital-logicflipflop
I have an excitation table that called MN flip flop like below.
Q Q' M N
0 0 0 X
0 1 1 X
1 0 X 0
1 1 X 1
I try to design a counter that count 0-7-2-3 in Proteus. In my estimation, this excitation table is like JK flip flop's excitation table and if I use not gate for K values, I find N values, is that possible like that converting? If not, how can I design flip flops like above that has excitation table for Proteus design. Any offers?
Thanks.
To make a T flip-flop, you take a D-flip flop and add feedback from the output to determine the next state.
The immage bellow shows the most basic operating logic of a T flip-flop. If you removed the feed back from Q and Q' you get a D flip-flop (And I know, you also have to invert the bit input on the lower and gate. Lets keep it simple, ok?)
So when you go to use a D flip-flop in a counter circuit instead of a T flip-flop, you have to manually add in the feedback that is now missing.
You mention that the table looks like a T flip flop. Is it possible you are interpreting the table incorrectly?
I believe the "QN" column represents "Q NOT", where the "Q" column is the value of Q resulting from the specific input. In this case, the table correctly represents the behavior of a D flip flop.
Best Answer
Build a state machine diagram. Figure out the patterns by which one state goes to the next. The inputs are the current state and any inputs, and the output is the next state. Then add the JK excitation that brings you to the next state. Make sure, at this point, that you have no duplicate states (i.e. states that with the same input that end up at all the same outputs) and eliminate them if you do. Once you have this, then start building Karnough maps for the outputs and JK excitations until you feel like you are ready to implement the resulting logic.