Pure address decoding logic.
The upper bits of the address bus are routed through logic, usually including things like '3-to-8 decoder' and the like to create a selection of "chip select" signals that connect to the different devices to activate them at different address ranges.
So for your example, the upper 2 bits of address bus could be linked to a 2-to-4 decoder to give the ranges 0x0000 to 0x3FFF, 0x4000 to 0x7FFF, 0x8000 to 0xBFFF and 0xC000 to 0xFFFF
The lower 14 bits will all be connected direct to all the devices (or as many as they need up to 14)
Within those ranges you could further split it down if you desired to make a finer-grained range.
Let's start with the word "word" (pun intended)
In this case it represents the default size of the storage medium of the system. This could be any number of bits, but was commonly 8 bits (in, for example the Z80 of the ZX Spectrum, etc), or 16 bits in the early PC systems (8086, 80286 etc).
So an 8 bit computer has a word size of 8 bits.
Then there are 16 address bits. This is literally the number of address lines on the chip. Again, taking the Z80 as an example, there were 16 of them (A0 to A15). This gives a possible \$2^{16}\$ addresses - 65536.
Each one of those addresses represents the memory location of one word of data.
That's 65535 available words - on an 8-bit system that's 64KBytes. On a 16-bit system it would be double that at 128KBytes.
Now, the RAM memory, the ROM memory, and (depending on the architecture) the IO peripherals will all take a number of those 65536 addresses.
Say for example you have 2K of ROM and 4K of RAM. That's 2048 addresses of ROM and 4096 addresses of RAM. Not all the addresses are used up, so there is room for memory expansion say.
The ZX Spectrum 48K had 16K of ROM and 48K of RAM for example. That's 16384 addresses pointing to ROM, and 49152 addresses pointing to RAM.
How much of the available 65536 addresses are actually used is purely down to the designer of the computer.
Best Answer
2GB of memory requires 31 address lines. This is because 2\$^{31}\$ = 2147483648 (see this page for powers of 2 values).
So this would require 31 address lines going from the microcontroller chip to the memory chip. (Microcontrollers usually have RAM memory built in, but not this much -- so an external memory chip must be used.)
In addition there would be data lines going from the memory chip to the processor, i.e. 32 data lines for a 32-bit processor, and 64 data lines for a 64-bit processor. There will also be some control lines on top of that.
If it is a 32-bit machine, then they are usually read out 32-bits, or 4 bytes at a time at a time. If only one byte is read out, it can be less efficient if it is not on a 4-byte boundary because a shift has to be done. Likewise for a 64-bit machine.
Because of the large number of lines going from external chips to the microcontroller, they are built with ball grid arrays (BGA) which allow for many hundreds of connections.