How to use NAND gates to divide (5bit) binary inputs by an integer (say 5)

We don't normally talk about a NAND gate having "state". It just responds to its inputs.

Since a NAND gate usually can respond to its inputs within a few nanoseconds, while power supply voltages typically take at least a few milliseconds to come up to valid levels during turn-on, the "state" of the NAND gates output immediately after start-up is rarely relevant.

In general during start-up there will be some time when the voltage rises to the point where the circuit is basically functional, but is not guaranteed to be functional. A NAND gate will start to respond to its inputs during this time and should be completely in sync with its inputs by the time the power supply voltage reaches the minimum voltage for guaranteed operation.

lets say a NAND gate for instance, and I send a 1 through input A, and a 1 through input B.....lets say (for some reason) the A gets there faster

This can happen, and it is called a "glitch". A typical case is when A is switching from 1 to 0 and B is switching from 0 to 1. The output to the prior inputs is 0, and the output to the final inputs is 0, but it's possible to see a 1 asserted for a brief time during the transition if the change in A arrives first.

This is why designing syncronous logic is in many ways simpler than designing combinatorial logic. In syncronous logic we can arrange the timing so that the next flip-flop downstream never has a clock edge arrive during the time when the upstream logic might glitch, so the glitch never propagates through to be seen at the final outputs of the system.

Possible reasons:

1. Load Balancing
   • The driver of A has an unknown number of fan-out to drive. Fan-out within the circuit and the parasitic it induces can be calculated for the specific circuits, but we do not know the other circuits that are connected the driver. Essentially the inverters are being used as buffer equivalent. and help manage the parasitic.
2. Timing and total current
   • To reduce the transition glitch, the second state inverters can be sized for a faster transition switch. Doing so makes the NAND gates input update near the same time. With the inputs changing less periodically, power can be saved and transition glitches can be reduced.
3. Signal boosting and power
   • Lets say VDD = 1.2V but the input is 0.9V. The input is still a logical 1, but considered weak which causes slower switching and burns more power. The first inverters can be sized to handle transitions better, making the voltage more predictable for the rest of the design.
   • There is also a possibility of the change in the voltage domain. In this case the inverters in the first state can act as a step down, e.g. a 5V input domain to 2V domain.
4. Any combination of the above