I am an Electronics & Comm. Engg. 3rd yr. student and we are learning CMOS logic for the first time this semester under the subject VLSI design.
While designing for the logic equation: \$Y= A + B.C\$, the professor first wrote it as \$\overline{\overline{A+B.C}}\$ , then simplified it by De Morgan's laws and then implemented it with CMOS.
I was wondering if it would be better to implement \$\overline{A+B.C}\$ and then use a CMOS inverter to invert to output since this would need lesser number of gates. When I asked the professor if it can be done that way, he said there won't be any sense in using CMOS if used that way. I didn't understand what this means, and why it cannot be implemented this way.
P.S. I'm new on Stack Exchange. Apologies for any mistakes in my way of putting the question.
Best Answer
When implemented in CMOS, simple inverting logic gates take one stage, that includes inverter, NAND, NOR.
Non-inverting logic gates take two stages. For example, a buffer would actually be two inverters back to back. An AND gate would actually be a NAND gate plus an inverter...
I assume your professor did the following:
\$Y = A + B * C = \overline{\overline{A} * (\overline{B * C})}\$
So the actual logic required are one inverter (for A), one NAND (for B,C), one NAND (final output).
If implemented as you suggested, it would actually be like:
\$Y = A + B * C = \overline{(\overline{A + \overline{(\overline{B * C})}})}\$
So it would be an inverter+NAND (for B,C), an inverter+NOR (final output).
So it takes one extra inverter -- not so bad in this case. But there is a big speed disadvantage, 4 levels vs 2.
This quote "he said there won't be any sense in using CMOS if used that way" may have lost something in translation. But I am guessing that your professor was trying to convey the fact that inverting logic gates are the natural building blocks of CMOS logic and are in general more efficient than the non-inverting counterparts.