ISA efficiency code compaction and memory traffic


I'm having issues understanding this problem and am new to ISA's. Here's a problem with 3 questions and my biggest question is, what is supposed to happen? Specifically, the HLL Code at the bottom.

Assume four ISAs

  1. accumulator-based
  2. stack-based
  3. memory-to-memory (operands located in main memory)
  4. register-based (pure load/store)

Instruction / data size

  • all data operands 4 bytes
  • all memory addresses are 16 bit
  • all opcodes 1 byte
  • memory address fields 2 bytes wide
  • register fields in load/store machine are 4 bits wide (16 32-bit registers)

Additionally, all memory addresses are 32-bits long and all instructions and data are fetched in one single memory access in the case of memory-memory architecture, no need to use additional memory location.

Compile code for four ISA's and determine the metrics: 1) code size 2) data memory traffic, including addresses, 3) instruction traffic, including addresses.

HLL code:

 A = B + A
 C = A - C + D

Best Answer

As a hint to get you started, here are some possible instruction sequences for the first HLL statement:


load A
add B
store A


load A
load B
store A

Memory-to-memory (2-address)

add B, A


load A, r1
load B, r2
add r2, r1
store r1, A

Your job is to figure out how big each instruction is, and also what the memory access patterns are for both instruction and data operations as each sequence executes.