JK Flip Flop toggle action

First, personally I would refer to the circuit you show as a set-reset flip-flop with enable, also called a latch. I reserve the words register and clock for an edge-activated two stage memory element.

The instable situation you sketch does exist and is called metastablility. It occurs when both of the set-rest flip-flop inputs were 1, and both switched to 0 at the same time. This causes a time period in which the outputs can show weird behavior, like oscillation or values half-way between 0 and 1. Eventually the flip-flop will settle to a stable situation, with one output 1 and the other 0. This metastable period is short, but IIRC its length follows some statistical distribution, so it has a non-zero (but very very small) chance of extending to any given length.

Current-day chips are generally synchronous internally, which avoid the metastable problem. It can still occur at the edges (external inputs), where it is usually eliminated (to a very high probability) with two flip-flop stages in series, where the second one is enabled only after the metastable period of the first is (very probably) over.

A flip-flop can only change state when there is a zero-to-one transition in the incoming clock. If J=1 and K=1, Q output will toggle at half the frequency of the CLK.

It may help you (or confuse you) to know that internally a flip-flop can be formed by cascading two level-sensitive latches, the first of which is low-level latching and the second one is high-level latching. When the same clock is fed to both latch enables, the first latch will settle its state when the clock signal (its latch enable) is low. The second latch will settle its state when the clock signal (its latch enable) is high. Note that the input of the second latch is the output of the first latch. The end result is an edge-sensitive device.