I am currently working on a little project and the goal is to find a new model for calculating FPGA's reliability.
I have been working with the MIL-HDBK-217F+N2, but when it comes to the complexity (number of gates) of a FPGA, it goes only until 60,000 gates. But nowadays the complexity can go to several million of gates.
Now my question is, is there any link between complexity and the reliability of a FPGA? Is a FPGA with a lot of gates not as reliable as a FPGA with less gates? And how is Moore's Law affecting reliability?
I have been trying to analyze data from FPGA manufacturers, in their reliability reports, but it seems that the only determining parameter of how they calculate the reliability (in FIT) of an IC is the "Device Hours". The longer the device is tested, the lower the FIT. Unless there is a failure of course. So I can't really compare different FPGAs because they don't have the same duration of testing.
I hope someone could clarify this for me! Thanks.
Best Answer
As integrated circuits get smaller feature sizes they get less of a risk from failure from single event upsets (SEUs). This is because the single transistor area is less, reducing the chance for a hit by a energetic particle. This makes modern FPGAS less vurnerable to SEUs.
FIT is usually specified as expected failures per billion hours of operating time. Of course different manufacturers have different testing scenarios, but the number they provide is the same. (yes?)
As an example, look at FPGA/CPLD Reliability from CERN. It is a nice source related to your question and how to make a more reliable system.
A FPGA with more logical units can provide more reliability and double or triple redundancy. With fewer logical units, you cannot do that. The complexity comes more from the designed functions, and not the architecture itself in my opinion.
I would say that a modern FPGA with more transistors can be more reliable than an older one. Because reliability is a design goal, and would not regress over time.