Understanding @(posedge) in Verilog

verilog

In the circuit below, I'm trying to count the number of clock pulses that happen while the decode signal is high. In order to do this, I create a composite wire that takes the AND of clk and decode, and increment a counter at the positive edges of this signal.

module countPulses(clk, decode);
  input clk;
  input decode;

  wire composite = clk & decode;
  
  reg  [15:0] composite_counter = 16'h0000;  // Increments too often
  reg  [15:0] delayed_counter   = 16'h0000;  // Lags 1 cycle behind desired
  reg  [15:0] desired           = 16'h0001;  // Intended counter behavior

  always @(posedge composite)
  begin
    composite_counter <= composite_counter + 1;
    desired <= desired + 1;
  end

  // Manually fix up the desired results on the falling edge of `decode`
  always @(negedge decode)
    desired <= desired - 1;

  always @(posedge clk)
    if (decode) delayed_counter <= delayed_counter + 1;

endmodule

Unfortunately, composite_counter doesn't work as I expected. I'm looking for the values shown in desired, but instead, composite_counter increments again at the falling edge of the decode signal. I don't understand why this happens, as you can see in the trace that when this occurs, composite and decode are both zero. There should be no overlap between the rising edge of clk and the falling edge of decode, but for some reason, it's being treated as a posedge anyways. I'm new to Verilog and hardware design, so perhaps I'm misunderstanding how @ posedge works.

I also tried incrementing a counter (delayed_counter) at posedge clk instead of posedge composite and checking if decode is high. This doesn't exhibit the double-counting behavior that composite_counter does, but the values are delayed one cycle from those in desired. I understand why this is happening, but wanted to point it out as a potential solution that won't work.

With that, my two questions are:

Why does always @(posedge composite) fire when composite is (and remains) zero?
How can I achieve the behavior shown by desired without resorting to such haphazard techniques as decrementing the counter on the falling edge of the decode signal?

Best Answer

You have a race condition between the falling edge of decode and the rising edge of clock.

Zoom in your wave viewer and you’ll probably see composite going high very briefly at that edge.

To fix it, make sure that decode goes low some nonzero time before clock goes high. Or, even better, instead of using a gated clock (google this term if you don’t know it), use decode as an enable signal, and clock as a clock.

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The code you showed has a few problems:

You don't show how error_count is declared in the top-level module. If error_count is just declared as wire error_count;, you only have a single bit of your counter connected between the counter module and the lcd module.
You don't show how the counter is updated in the counter module. You could have a bug there that results in the counter never updating. Since it is initialized to 0, you'd always have a 0 output from the counter module.
You don't show any clock input to the counter module. If clock is not connected, error_counter will never be updated.
You say that lcd has a clock input, but you don't show that it actually does, and you don't show any code where it matters.
You don't show how your clock is generated. If there's no clock, the counter won't updated.
You don't show the complete input and output ports to either module. With your coding style it's easy to connect a wrong input to a wrong port. I much prefer to intantiate modules with the syntax like

counter counter1 ( .clk( clock ) , .error_count( error_count ) );

With this style, the order of naming the in's and out's in the instantiation doesn't matter.
You haven't shown any reset signal, but you probably have one. If the reset is stuck in the active state, probably the error_count won't ever increment.

How to solve ERROR Xst:528 in ISE

You are assigning the cnt_## signals in more than one always block. This is not allowed and results in a multiple driver error.

The code in question

always @(posedge clk)                   
    if(rst) begin               
        state = S0;         
        cnt_12 = 5'd20;         
        cnt_23 = 3'd5;          
        cnt_34 = 5'd25;         
        cnt_40 = 3'd5;          
    end else                
        state = state_n;            

always @(negedge clk)

Always put begin and end around things - even if strictly not necessary. It makes things far clearer and stops mistakes like this.

always @(posedge clk) begin                 
    if(rst) begin               
        state = S0;         
        cnt_12 = 5'd20;         
        cnt_23 = 3'd5;          
        cnt_34 = 5'd25;         
        cnt_40 = 3'd5;          
    end else begin              
        state = state_n;            
    end
end

always @(negedge clk) begin
...
        cnt_12 = 5'd20;
...
end

Notice how the variable exists in two always blocks? This is never allowed.

You are also not allowed to clock a register with both a negative edge and a positive edge. Dual-Edge flip-flops do not exist is most FPGAs.

Best Answer

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