I was reading about master-slave flip flops, used to implement edge triggering and I read that instead of using master slave configurations, using RC coupling to clock inputs could also enable pulse transition. How is this possible?
Using capacitive coupling to implement pulse transition
digital-logicflipflop
Related Topic
- Electronic – How to add reset functionality to a master-slave D-type flip-flop
- Electrical – Master-Slave D-FF vs Edge triggered: timing issues, simulation shoot-through
- Electronic – history of edge-triggered D flip-flop design using three S-R latches
- Electronic – State Machine with D Flip Flops; how to deal with race conditions
- Electronic – Confusion about when a JK flip flop is triggered
Best Answer
Your question is a bit vague — can you provide a specific example?
But in any case, the general concept is that an RC high-pass filter will convert a rising edge into a narrow positive pulse and a falling edge into a negative pulse. The negative pulses can be inverted to create a second set of positive pulses that's offset in time. Essentially, you end up creating a "local" 2-phase pulse-type clock out of the original single-phase square-wave clock.
In older logic technologies (think vacuum tubes), it was possible to "tune" the pulse widths so that data would propagate through just one flip-flop during one pulse duration, so multi-phase clocks were not necessary. However, as systems became larger and more complex, and we moved on to newer technologies (solid state) whose characteristics were less well-controlled, this approach had to be abandoned as unworkable. Multi-phase clocks became common (up through the first generation of IC microprocessors), and eventually, we switched entirely to master-slave flip-flops, which allowed us to migrate to single-phase square-wave clocks, simplifying clock generation and distribution.