Verilog: sampling data in both posedge and negedge of the clock

clockverilog

I have a serial input stream which has left data in posedge of the clock, and right data in negedge of the clock.

I would like to synchronize and bring them to the posedge of the same clock.

I could do that using another clock with twice of the frequency.

How to synchronize the data using the same clock?

Best Answer

Use the negedge of the clock to sample the "right" data and store it to a register, then use the posedge to sample the "left" data and the register.

reg r;
always @(negedge clock) begin
    r <= right_data;
end

always @(posedge clock) begin
    // use left_data and r here
end
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