Vivado Integrated Logic Analyzer Waveform empty

The problem is that pdm_clk isn't a port, it's a wire, and so won't be found by the get_ports search.

What you should instead do, is target the actual register driving the signal. You can do this with something like (haven't checked):

create_generated_clock ... {pdm_clk_div|clk_out}

Where in this case clk_out is the name of the register inside the ```pdm_clk_div` instance which is driving the clock net.

If the above doesn't work, you can try something like [get_pins {pdm_clk_div|clk_out}] or [get_registers {pdm_clk_div|clk_out}]

As a side note, if you are generating your own clocks, you should also include a BUFG primitive on the output so that the clock can be promoted to the global clock network. This will avoid excessive skew warnings later on during fitting.

However I agree with @johnnymopo's comment that the best approach is to use the original clock to drive your registers and then use the clock divider to generate a clock enable. Instead of generated clock constraints in this case you may instead require multicycle paths to declared if there are any timing issues.

Not sure if there is a way to do this with the ILA directly. My guess is probably not to keep the complexity of the ILA logic down. What I would recommend is writing a little bit of additional logic to generate a new trigger signal based off of this specific condition that you're looking for, and then use that signal to trigger the ILA. Should only take a few extra lines of HDL to generate the trigger signal you need; either a one-shot timer setup to generate a delayed trigger or something to swallow the first (or perhaps every other) tuser pulse. Probably the simplest circuit would be to simply toggle a level on every tuser pulse, then you can pick which one you want by changing the trigger slope (rising or falling).