I just finished to write a pretty complete design on ISE 14.7 targetting a Virtex7 device. The behavioural simulation (on Isim) takes a while but works perfectly.
Therefore, I tried to move to the next step adding a Time Constraint by double clicking on my top module -> User Constraints -> Create Timing Constraints in the ISE interface. This action triggered the synthesis and it's now more than 24 hours that ISE is trying to "Optimize" one of my module.
I don't mind about letting the program running for other 24 or 48 hours but I am suspecting that something is wrong with my design … I know that it might be pretty eavy since I use many logic cores instances but I am afraid it doesn't justify the delay for the synthesis.
My design can be found at the following link:
https://dl.dropboxusercontent.com/u/12734577/fourier_QAM_modulator.zip
Does anyone have an idea about how to solve my problem ?
I thank you in advance,
Best regards
Edit:
For posteriority, the full code is available here; details and explanations can be found in the paper.
Best Answer
I finally solved my problem and I post my answer here for futur generations.
Consistently to the advice of Brian Drummond, I created a small testbench for each module of my system and I ran the synthesis as well as the post-synthesis simulation on each on of them. Everything was working fine, none of the synthesis were taking an excessive amount of time.
Subsequently, since my device contains a large number of loops, I have made the following modifications: - removing some input/output pins by using serialisation instead - configuring the IP cores to use DSP instead of the fabric
My design could finally synthesise after a large amount of time.
I hope this may help someone else