rtlsynthesisvirtex-series-fpgaxilinx
I did verilog code of a circuit. It was simulating well and giving output correct after Simulation. Now i did synthesis, the RTL schematic after synthesis showing some green and red box. Is it indicating any kind of error?
Please give any comment to clear this confusion.
Thank you.
Asking about the red and green boxes which i highlight using white color lines.
Add (and use) a reset signal.
Xilinx FPGAs have a global set/reset (GSR) signal that puts all registers in the their default state or as specified in the register declaration (this is documented in the XST User's Guide at the beginning of chapter 5). AFAIK, the @initial block is ignored.
However, things are chaotic when the FPGA starts up, because:
So the initial Flip-Flop values after the GSR are not enough.
Create a module that generates a reset signal for each clock domain. You can create it by by AND'ing relevant asynchronous reset signals, such as an external reset pin, PLL/DCM locked signals, and using it with a synchronizer, as follows:
(Source: How do I reset my FPGA?)
You have to run the generate_timing report on your design to get the detailed report for your design. In ISE you do it by choosing Tools->Timing-Analyzer->PostMap
It will generate a report with the information you asked for.
For more accurate timing analysis of your design, you should look into the timing AFTER the P&R is done.
Best Answer
There is no error.
Green Box: start of a wire.
Red Box: end of a wire.
I don't know why ISE's RTL viewer shows these boxes. Inputs and outputs are defined by the right and left side of sub-schematic...