An error in using FIFO block in system generator

errorfifofpgaxilinx system generator

I have designed a circuit in System Generator. I want to put a FIFO at the output before out gateway as shown in the below picture

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When I run it I face to the following error

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I should connect the we and re pins to a clock, hence I set clock probe at their inputs. I do not know where is wrong. Can any one help me in driving these two input ports of FIFO?

Best Answer

You are geting the error because you can't connect clock probe to a system generator block. But appart of that, what you are doing in this scheme, is the same of getting the WE and RE connected to '1' ! If your idea is connect 2 different clock domains, this is done with the clock signal inputs, that dont appear in sysgen blocks on simulink. But you can simulate this with constants in WE and RE, with diferent Rates.

Related Solutions

Electronic – Pipelining and clock frequency issue

Your design will not function correctly if it runs at 100 MHz but is only spec'd (by the tools) to run at 50 MHz. If it does, then it's a one-off miracle that wouldn't work when you make a change and rerun the tools. Don't do it. Don't even do it if your clock is 100 MHz and the tools tell you the design can run at 99.5 MHz.

To solve your problem you can either write a simple 'divide by power of 2' clock divider to reduce the clock frequency (something like this in Verilog):

reg [n:0] count; 

always @(posedge CLK_100) begin
  count <= count + 1;
end

BUFG bg_0 (.I(count[m]), .O(CLK_DIV));

(where 'm' <= 'n' and 'bufg' is a global clock buffer, and must be used for synchronous designs) or use a Digital Clock Manager (DCM).

Hopefully that solves your pipelining issues as well unless you absolutely have to run the entire design at 100 MHz. Other than pipelining you can consider using FIFOs if you have part of the design running at 50 MHz and the other at 100 MHz, but you'll have to say a bit more about what you're doing to get more meaningful help here.

System generator frequency issue

Im not an expert on this but a little research (30seconds) on our favorite search enginge brought me to someone who had the exact same problem 5 years ago. I think you can go on from there, eventhough the frequency is a little different. http://www.velocityreviews.com/forums/t294219-frequency-divider.html

Best Answer

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Electronic – Pipelining and clock frequency issue

System generator frequency issue

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