I have designed a circuit in system generator. I am using a FIFO at the output. I want to connect the we pin of FIFO to the clock of FPGA, but I do not know how should I do it in System Generator. In another language how can I access to the clock of FPGA in System Generator. Can anyone help me?
Using the clock of FPGA in system generator
clockfifofpgaxilinx system generator
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Best Answer
I have seen at least two ways to use System Generator:
I'm not sure if what you're asking is possible if you're using method 1. However if you're using method 2, you can always connect the we input of the FIFO to a yellow input block, then when you place your auto-generated VHDL component into your top-level design, you can tie the clock to the we port you created.