I have a circuit in system generator which I cannot retrieve the output signal since it has a high rate. For this issue I planned to use a FIFO at the output. I wanna give the circuit clock to write-enable pin and give read-enable pin a clock with more frequency. So I want to slow down the clock of FPGA, give it to to my previous circuit and then give the clock of FPGA to read-enable pin of FIFO. I asked some days ago and someone taught me using a counter for this issue. So my problem is to decrease the frequency of FPGA's clock by using a counter. I will be thankful if someone give me a picture of the circuit drawn in system generator for this manner.
Electronic – making different clocks in system generator
xilinxxilinx system generator
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Best Answer
You can get 1000 by using two of these: -
Note that it can be configured to divide its input frequency by either 10 or 100. Putting two of these in series will produce a total clock frequency divider of 1000. If 1024 can be used then it's even easier because \$2^{10}\$ is 1024 so you need a ten stage ripple counter such as the 74HC4040 (OK it happens to have 12 stages but just ignore the outputs from stage 11 and 12). Power for both types is between 2V and 6V and don't forget to provide a 100nF power decoupling capacitor on the power rails at the chip.
For clock frequencies over 1GHz: -
At the further end of the scale, if you had clock frequencies over 1GHz then there is the AD9515 - it can be set to divide by 10 and you'd need two (or possibly one followed by some very fast "normal" CMOS divider). The AD9515 is also a dual counter with a common input clock suitable for LVDS or PECL etc - it can be coupled capacitively.
D type divider for use in xilinx system generator: -
Q0 is CLOCK divided by 2 - each subsequent D type divides the clock by a further two. Q2 is clock divided by 4. Cascade 10 D types as shown above to get divide by 1024 or \$2^{10}\$.