System generator frequency issue

Your design will not function correctly if it runs at 100 MHz but is only spec'd (by the tools) to run at 50 MHz. If it does, then it's a one-off miracle that wouldn't work when you make a change and rerun the tools. Don't do it. Don't even do it if your clock is 100 MHz and the tools tell you the design can run at 99.5 MHz.

To solve your problem you can either write a simple 'divide by power of 2' clock divider to reduce the clock frequency (something like this in Verilog):

reg [n:0] count; 

always @(posedge CLK_100) begin
  count <= count + 1;
end

BUFG bg_0 (.I(count[m]), .O(CLK_DIV));

(where 'm' <= 'n' and 'bufg' is a global clock buffer, and must be used for synchronous designs) or use a Digital Clock Manager (DCM).

Hopefully that solves your pipelining issues as well unless you absolutely have to run the entire design at 100 MHz. Other than pipelining you can consider using FIFOs if you have part of the design running at 50 MHz and the other at 100 MHz, but you'll have to say a bit more about what you're doing to get more meaningful help here.

You can get 1000 by using two of these: -

Note that it can be configured to divide its input frequency by either 10 or 100. Putting two of these in series will produce a total clock frequency divider of 1000. If 1024 can be used then it's even easier because \$2^{10}\$ is 1024 so you need a ten stage ripple counter such as the 74HC4040 (OK it happens to have 12 stages but just ignore the outputs from stage 11 and 12). Power for both types is between 2V and 6V and don't forget to provide a 100nF power decoupling capacitor on the power rails at the chip.

For clock frequencies over 1GHz: -

At the further end of the scale, if you had clock frequencies over 1GHz then there is the AD9515 - it can be set to divide by 10 and you'd need two (or possibly one followed by some very fast "normal" CMOS divider). The AD9515 is also a dual counter with a common input clock suitable for LVDS or PECL etc - it can be coupled capacitively.

D type divider for use in xilinx system generator: -

Q0 is CLOCK divided by 2 - each subsequent D type divides the clock by a further two. Q2 is clock divided by 4. Cascade 10 D types as shown above to get divide by 1024 or \$2^{10}\$.