Electronic – System Generator: How to generate a .bit file

From the latency on the cordic block, that looks as if you've chosen to use a single processing element - that will produce results of limited accuracy. Very limited it appears :)

I tried using 10 elements for example, with [zeros (1,9) 1] for the "latency per processing element" - to get back to your 21 tick latency. Making sure I ran the simulation long enough (oops), I then got a result (using UFixed_16_11 inputs) of 0.501953125. Which is closer...

Does that help?

If you double-click the Gateway block and click to the "implementation" tab, there's a box you can tick to "Specify IOB location constraints".

You can then enter something like this in the IOB pad locations box underneath:

{'P22', 'P12'}

(if you have 2 bits, repeat as needed if you have more!). This is for a leaded package with simple numbers on each pin. If you're using a BGA device, the pins will be named alphanumerically. It's explained quite well in the HELP for the Gateway blocks.

You can check this has worked by looking at the .pad file in the same directory as your .bit file was created - you should be able to find the IOBs named and see which pin they were mapped to. (There's two versions of the pad file, one is a CSV file the other is a text table which looks fine in a monospaced font)