Electrical – Help understanding SR Flip-Flop

You can work it out by going through the steps.
We know if T is at 1 then Q will toggle, if it's at 0 Q will stay the same.

Say we start off with Q0, Q1 and Q2 at 0, and the multiplexer input is set to 0 (so basically ignore the Qbar paths)

At the first clock pulse, since T0 is at 1, then Q0 will toggle from 0 to 1.
So we now have 1 0 0
At the second clock, since T1 is at 1, Q1 will toggle from 0 to 1. Q0 will toggle back to 0.
Now we have 0 1 0
At the third clock, Q1 will remain at 1 since T1 is at 0. Q0 will toggle back to 1.
Now we have 1 1 0
At the fourth clock, since the and gate now has both inputs (Q0 and Q1) at 1, then T2 will be at 1 therefore Q2 will toggle from 0 to 1. T1 is at one so Q1 will toggle back to 0, as will Q0.
Now we have 0 0 1
At the fifth clock, T2 = 0 so Q2 will remain at 1, T1 = 0 so Q1 stays at 0, and Q0 always toggles so it will change to 1.
Now we have 1 0 1
At the sixth clock, T2 = 0 so Q2 stays at 1, T1 = 1 so Q1 toggles to 1 and Q0 toggles to 0.
Now we have 0 1 1
At the seventh clock, T2 = 0 so Q2 stays at 1, T1 = 0 so Q1 stays at 1, and Q0 toggles to 1.
Now we have 1 1 1
At the eighth clock, both inputs to the and gate are high so T2 = 1, so Q2 toggles to 0. T1 is at 1 so Q1 toggles to 0, and Q0 toggles to 0.
Now we have 0 0 0 which is where we started.
If you change the multiplexer input to 1 and select the Qbar path, you can see how it would count down (just complement all the above results, e.g. 0 0 0 becomes 1 1 1, 1 0 0 becomes 0 1 1 and so on)

Try starting to think from the second line.

If you put 0 to S port, it would go to 0 in the output regardless of the other input because it is an AND port. But its output is inverted since it is and NAND port, so when you put 0 in S signal, its output will necessarily goes to 1 regardless of the other NAND input.

Therefore, one of the lower NAND port inputs will be 1. Since we are in the second line of the truth table, R should be 1. So the lower NAND port will have both inputs in one (H). So its output will necessarily be zero. Then you have Q = 1 and Q! = 0.

If you make the same reasoning for the third line, you get correct results since it is the symmetrical situation.

As for the first line, you cant have correct results. Note that if we put 0 to S, we have Q = 1 (as the second line of the table). Altough if you put zero to R too, you will also have Q! = 1. This situation is called disallowed because Q should complement Q!. They always have to be different signals.

And for the last line, imagine we are in the second line again so we have Q = 1 and Q! = 0. If we put S to 1 (it was zero before), note that Q! is already zero, so changing S signal will not change the first NAND port result. So whenever you are in states 2 or 3 (second or third line), placing 1 to any of the inputs that are low, will not change the state.