Electrical – How to fix pin assignments on a Quartus Prime Lite project

I am using Quartus Prime Lite Edition 16.02 and am trying to fix messed-up pin assignments for a simple project with a single verilog file:

module mux4( input  a, b, c, d,
             input [1:0] sel,
             output out );
  wire t0, t1;
  assign out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
  assign t1  = ~( (sel[1] & d) | (~sel[1] & b) );
  assign t0  = ~( (sel[1] & c) | (~sel[1] & a) );
endmodule 

In the past, I've assigned nodes a, b, c, d, sel[1], and sel[0] to SW[0], SW[1], SW[2], SW[3], SW[4], and SW[5], respectively, and I've assigned node out to LEDR[0]. Since changing the verilog file, however, I've been unable to get pin assignments to work.

I tried the following:

1. I deleted the .qsf file from the project directory (through the
   file system).
2. I selected Assignments > Import Assignments and imported
   DE1_SoC.qsf.
3. When I open the assignment editor, the pins to which I had assigned nodes show up with question marks in their status column:
   In the bottom of the assignment editor, I see my earlier pin assignments:
4. I start a compile.

I get these messages:

Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Error (171016): Can't place node "c" -- illegal location assignment PIN_AF9
Error (171016): Can't place node "b" -- illegal location assignment PIN_AC12
Error (171016): Can't place node "d" -- illegal location assignment PIN_AF10
Error (171016): Can't place node "sel[1]" -- illegal location assignment PIN_AD12
Error (171016): Can't place node "sel[0]" -- illegal location assignment PIN_AD11
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:00
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error: Quartus Prime Fitter was unsuccessful. 6 errors, 3 warnings

I was able to simulate this design in the past. What do I need to do to get it working again?