"Lets consider a SR Latch built with NOR gates. The invalid inputs are S=1, R=1. With enabled latch [gated latch], the invalid inputs are same, S=1, R=1."
That is true only when the gating does not invert the signal (for instance two AND gates).
"Now, lets consider, NAND gates, in SR Latch, the invalid inputs are S=0, R=0. But in enabled SR latch, the invalid inputs are S=1, R=1"
Correct, because the gating inverts the S and R signals.
"So, can I say, invalid inputs with SR Latch with NAND are: S=1, R=1"
Correct
"If enabled, then S=0, R=0"
That is half-true. You should be able to formulate the fully-true answer by yourself.
A D flip flop simply latches the value of a wire on it's D pin at the rising edge of a clock. Using three inputs (S, R, and Q (output of the DFF)), you need to create a small combinational circuit which mimics an SR flop:
- If
S is set, the value of D should be 1
- If
R is set, the value of D should be 0
- If neither is set, the value of
D should be Q
With these three statements it's simple to create a small truth table and from that to create the combinational circuit which should drive your D pin.
Best Answer
The two are different because the first doesn't show the internal structure of the SR latch, and it is hooked up in reverse of the second example. The first example is concerned entirely with the logic of the latch, while the second is concerned with the gate connectivity.
That is, in both cases, a high enable, a high set and a low reset will both cause Q to go high. It's just that, in the first example the set input and Q output are at the top, and a high at the top input will cause a high on the top output. Most beginners find this sort of organization easier to understand. In the second case, a high on the top input will cause the bottom output to go high. When you show all the gates, it's easy enough to see how this works, but it's less spatially intuitive. If it helps, the complete circuit for the first example is
simulate this circuit – Schematic created using CircuitLab