Electronic – Aldec Active-HDL – No Default Binding

Can you clarify what HDL you want to use? The choices are basically Verilog or VHDL, [EDIT], and their relatives, Verilog-ASM and VHDL-ASM (Analog mixed-signal). [/EDIT]Verilog has some C-like syntax, which makes it easier to pick up if you've worked with C before, but this also makes it easy to develop bad habits - You can't program hardware in C, because it's all parallel! Also like C, it assumes you know what you're doing, and it's easy to shoot yourself in the foot. VHDL forces you to think in a totally different way, which is helpful, but difficult. It is more verbose, and more likely to warn you if you do something strange. See this Slashdot discussion, or this article.

EDIT: The "Netlist languages" are not something I've used for design work (in a text editor), but I suppose that you could. SPICE, Cadsoft Eagle's format, and EDIF are all examples (with very different purposes) that come to mind. I've only used netlists to verify that my schematic is correct (does each connection in my Eagle schematic make sense), to tweak the abstraction provided by a simulator (SPICE, similar to the way one uses ASM statements in C), or to do export/import between different programs (EDIF).
The Spectre netlisting language is related to Verilog-A[nalog] and SPICE, and is designed for design and verification work. MAST is a component modeling language which is compatible with Verilog-AMS and VHDL-AMS. Searching for tutorials on these languages shows that tools which look like schematic capture utilities are often used, rather than programming in the netlisting language itself.

I'll also second the Xilinx Spartan FPGA, and a Digilent dev board. However, I'd go with the Basys ($60) or Nexys ($100) if you don't need the Ethernet on the Starter board ($150) mentioned by O Engenheiro (Prices with education discount). The Basys and Nexys are cheaper and therefore more popular in schools, so there are more tutorials and labs online.

The only files I check into my repositories are the VHDL source plus benches and adf files. All the others are automatically created.

I just add the adf files to a new workspace. I always put the VHDL source in a src folder in the same folder as the adf file.

I can't recall what files define the waveform view if you want to preserve that too. Aldec changed their waveform viewer (for the worst IMO) and I've not used it much since as I've not worked in a place lucky enough to own it.