Capacitor for J-K Flip Flop – Triggering Negative Edge Clock with Capacitor

capacitorclockdcflipflop

I have some SN74LS73AN Flip-Flops which, if I understanding well, are triggered by the negative (falling) edge signal of a clock.
I wish to use a simple pushbutton as a clock, and I am aware that, for a clean (debounced) clock signal, a capacitor is needed.
I'm using a 5v DC powered breadboard and a SN74LS73AN J-F Flip Flop.
What kind of capacitor should I get?
Thank you.

Best Answer

"Negative edge" doesn't mean a negative voltage. A negative voltage is a bad thing for most digital circuits.

"Negative edge" means the falling edge of the clock pulse. That is, the transition from high to low.

This is a negative edge:

enter image description here

That's a 1kHz square wave. It varies between 0 and 4V at 1kHz.

You don't need a capacitor to make a negative edge. You just need to make a falling edge.

You make a falling edge like this:

schematic

simulate this circuit – Schematic created using CircuitLab

When you push the button, the clock goes from high to low. When you release the button, the clock goes from low to high.

There's just one problem with that.

Buttons don't switch cleanly. When you push the button in a real circuit, the clock will look like this:

enter image description here

Over to the left, the output starts out high. The button is pressed, and the contacts bounce several times before the output finally goes low and stays there over at the right side.

Every zig-zag is another pulse for the J-K clock input. Pushing the button once will generate a whole bunch of clock pulse instead of just the one you want.

If you were using a microcontroller, you would write a simple debouncing routine to ignore the short pulses.

Since you are using a 7473, you'll have to debounce the switch in hardware - and here at last you will need a capacitor.

To debounce the button, you would modify the circuit like this:

schematic

simulate this circuit

With the additional resistor and the capacitor, the falling edge looks like this:

enter image description here

The clock drops fast over on the left edge on the first contact. The capacitor and the resistors prevent it from rising on the bounces. Over to the right, the pulse is completed.

You'll get one pulse on each press of the button just like you wanted.

R1 is a pull up resistor. It holds the clock signal high all the time.

C1 is there to remove the bounces. Together with R1, C1 forms a low pass filter with a time constant of about 10 milliseconds. Anything that "moves faster" than that gets filtered out. The bounce in the first button circuit was over after about 1.5 milliseconds. The 10 millisecond time constant is slow enough to remove those fast bounces.

R2 is there to limit the discharge current from the capacitor. A dead short circuit of a capacitor can cause a lot of current to flow. 100 ohms is low enough to quickly discharge the capacitor, but still not be a dead short circuit.