This is probably a simple question but how come CMOS Logic Gates built from Only Transistors is completely different from one that uses TTL Logic (Like BJT's). I know BJT aren't really used anymore because they consume power when they are "on" as compared to the low amount CMOS used…..but shouldn't the "Schematic" to produce a Gate be the same?
Electronic – CMOS vs TTL Logic Gates
cmostransistorsttl
Related Solutions
The first comprehensive logic series was the TTL series 74xx. This used BJTs (Bipolar Junction Transistors). Later there came variants like the often used 74LSxx, where the "LS" stands for Low-power Schottky TTL. As the name implies these used less power than the rather power-hungry TTL, and were faster too. At the same time the CMOS 4000 series was developed. The "C" in CMOS stands for Complementary, meaning it's a combination of N-channel and P-channel MOSFETs. Their construction is simpler than TTL and they use far less power. Later standard CMOS developed into HCMOS, "H" for High-speed. Most 74LSxx types have been released as HCMOS in the 74HCxx series, or the 74HCTxx series, which is TTL compatible. Later more variants were developed, like Advanced CMOS (74ACxx).
Microcontrollers are built in HCMOS technology, so they use MOSFETs. AFAIK JFETs aren't used for logic ICs. The transistor you show in the picture is a BJT, which you can tell from the pin designation:
E = Emitter
B = Base
C = Collector
For a MOSFET the pins would be
S = Source
G = Gate
D = Drain
respectively.
Many ICs in the 74HCxx series were originally released in 14 or 16 pin DIL packages, which meant that they would fit four 2-input gates. With miniaturization (SMT) came the demand for smaller packages, even if they contained less gates. Several manufacturers offer single-gate and dual-gate versions of logic gates. For example, NXP has a 74LVC1G00 (single 2-input NAND) and a 74LVC2G00 (dual 2-input NAND) version of the classical 74HC00. 74LVCxx is yet another HCMOS technology. This page lists all NXP logic families.
It is very likely CPU's and SoC's are used by hardware description languages like Verilog and VHDL (two major players).
These languages allow different levels of abstractions. In VHDL, you can define logic blocks as entities; it contains inputs and output ports. Within the block you can define the logic required. Say you define a block with input A, input B and output C. You could easily write C = A and B;, and basically you created a AND port block. This is possibly the simplest block you can imagine.
Digital systems are typically designed with a strong hierarchy. One may start 'top-level' with major functions a CPU requires: proccesor (multiple?) memory, PCI-express, and other busses. Within this level busses and communication signals between memory and procesor may already be defined.
When you step one level down, it will define the innerworkings of making something 'work'. Taken an example of a microcontroller, it may contain an UART interface. The actual logic required to make a functional UART is defined one level below.. In here, much other logic may be required to generate and divide the required clock, buffer data (FIFO buffers), report data to the CPU (some kind of bus system).
The interesting thing of VHDL and digital design is the reuse of blocks. You could for example, just copy&paste the UART block in your top-level to create 2 UARTs (well, maybe not that easy, only if the UART block is capable of somekind of addressing!).
This design isn't any kind of gate-level design. The VHDL can be also be 'compiled' in a way that it is finally translated to logic gates. A machine can optimize this far better than a human could (and quicker too). For example; the internals of block A requires an inverter before outputting the signal. Block B takes this output signal and inverts it once again. Well, 2 inverters in series don't do much right? Correct, so you can just as well leave them out. However, in the 'top-level' design you won't be able to spot the two inverters in series.. you just see two ports connected. A compiler can optimize this far quicker than a human.
Basically what digital system design contains is the description how the logic should 'behave', and the computer is used to figure out what the most efficient way is to lay out the individual logic gates.
Best Answer
No, the circuit structures to produce gates in TTL and CMOS are very different.
It's actually a very complex topic, because at this level, you can't just treat transistors (BJTs or FETs) as simple "switches". It becomes an analog circuit design problem in which many issues need to be considered: how static and dynamic currents flow, where charges are stored on the various internal "nodes", connectivity among gates (fan-in and fan-out), etc.
Also, different types of transistor technology have different ways in which they can be applied. "True" TTL (74xx, 74Lxx, 74Hxx, 74Sxx) uses a single multi-emitter transistor to create a basic NAND structure with an arbitrary number of inputs; the rest of the circuitry is basically buffers so that the gate can drive the next gate(s) downstream.
LSTTL is really an advanced form of DTL (diode-transistor logic), in which the basic structure is an AND gate; again, the transistors are mainly for buffering.
In CMOS, the basic structure is a 2-transistor inverter. To create other logic functions, additional transistors are added in series/parallel with the original pullup/pulldown transistors of the inverter. Ideally, there is no static current draw at all, just the dynamic current of charging and discharging gate capacitances.
PMOS and NMOS were never offered as standardized gates in SSI/MSI packages, but these technologies were widely used in custom IC design for quite a while. The basic gate structure is basically half a CMOS gate, but with a passive pullup (a transistor used as a current source) as a load. All of the early microprocessor chips were built with these technologies.
Any technology based on MOS transistors has very high input impedances, which means that charge storage is a viable way of remembering data values, at least for short time periods. This can save a lot of transistors, and is why most early microprocessors had minimum as well as maximum clock frequencies. This technique can't be used with BJT technology.