Electronic – Should I use CMOS vs. TTL

No, the circuit structures to produce gates in TTL and CMOS are very different.

It's actually a very complex topic, because at this level, you can't just treat transistors (BJTs or FETs) as simple "switches". It becomes an analog circuit design problem in which many issues need to be considered: how static and dynamic currents flow, where charges are stored on the various internal "nodes", connectivity among gates (fan-in and fan-out), etc.

Also, different types of transistor technology have different ways in which they can be applied. "True" TTL (74xx, 74Lxx, 74Hxx, 74Sxx) uses a single multi-emitter transistor to create a basic NAND structure with an arbitrary number of inputs; the rest of the circuitry is basically buffers so that the gate can drive the next gate(s) downstream.

LSTTL is really an advanced form of DTL (diode-transistor logic), in which the basic structure is an AND gate; again, the transistors are mainly for buffering.

In CMOS, the basic structure is a 2-transistor inverter. To create other logic functions, additional transistors are added in series/parallel with the original pullup/pulldown transistors of the inverter. Ideally, there is no static current draw at all, just the dynamic current of charging and discharging gate capacitances.

PMOS and NMOS were never offered as standardized gates in SSI/MSI packages, but these technologies were widely used in custom IC design for quite a while. The basic gate structure is basically half a CMOS gate, but with a passive pullup (a transistor used as a current source) as a load. All of the early microprocessor chips were built with these technologies.

Any technology based on MOS transistors has very high input impedances, which means that charge storage is a viable way of remembering data values, at least for short time periods. This can save a lot of transistors, and is why most early microprocessors had minimum as well as maximum clock frequencies. This technique can't be used with BJT technology.

First off, take that book, douse it in gasoline/petrol and burn it. Secondly, saying that something is CMOS is akin to saying that something is a circuit. There are so many variants ... Even 25 to 30 years ago CMOS ASIC flows (Gate arrays, or Sea of Gates) approaches were already way faster than any of the discrete forms of logic (AS, LS etc.). You first saw discrete logic chips that then integrated more transistors, these became known as MSI (Medium Scale integration) designs (like UARTS etc.) that may have been built on similar CMOS processes. But by the time that LSI (large scale integration) designs started to come out the processes for discrete and integrated CMOS had bifurcated and diverged. Probably at the 3 um node LSI and VLSI (Very large scale integration) design never looked back. Microprocessor processes (also CMOS) had their own design methodology and techniques.

Even at the time of publishing that book had it wrong. We were in the midst of the latest 0.13um process technology, worrying about scaling effects and yield in these new radically smaller transistors. Going from 2 um to now 20 nm (arms fully waving now) which is a factor of 100X and a scaling according to Moore's law of sqrt(2) roughly translates into 14 generations of scaling /changes.

Just to give to perspective, in 0.18 um process technology you can build a pretty sweet op-amp that has a unity gain bandwidth of about 1.2 GHz (0.8 ns) which is good for 14 bits SNR. This is CMOS technology that dates back to the late 1990's.

If I recall correctly, you could build 2 GHz logic designs in 0.13um processes with full clock trees and fan out quite nicely.