Electronic – Configure Quartus 2 Simulator to run for longer

Despite the "reg" declaration in the source code, you have not in fact created any registers. The behavior of your 3000-bit "data" bus is simply that its value is a function of the current value of the "button" input; it doesn't depend on the past history of that or any other signal, so there's no actual memory behavior specified, and therefore no synthesizable flip-flops.

The only logic here is a simple inverter, the output of which is replicated 3000 times. Since nothing is connected to the "data" bus (and it isn't even specified as an output port of the module), there's no need to implement logic to support the fanout, and in fact, there's no need to implement the inverter at all. What is it you're actually trying to debug? By what mechanism were you hoping to observe the data bus?

I'm guessing that Xilinx took an ultra-conservative approach and actually implemented 3000 inverters. I have no idea why it would do that. The answer may have something to do with the actual debug mechanisms that each manufacturer builds into its chips.

If you're trying to measure things like power consumption for various levels of FPGA utilization, the usual technique for this is to create a long shift register. The register is clocked by common clock signal (usually a global clock) and the input of the first bit and the output of the last bit are brought out to pins (the latter is so that the synthesis software doesn't "prune" away the entire chain).

You control the amount of resouce utilization by varying the length of the shift register, and you control the amount of switching activity by the pattern that you shift into it. A pattern of all zeros or all ones eventually has the minimum activity, while a pattern of alternating ones and zeros eventually ramps up to the maximum level of activity.

module shift (clk, si, so);
  parameter SHIFT_LENGTH = 3000;
  input     clk, si;
  output    so;
  reg    [SHIFT_LENGTH-1:0] data;
  always @(posedge clk) begin
    data <= {data[SHIFT_LENGTH-2:0], si};
  end
  assign so = data[SHIFT_LENGTH-1];
endmodule

After you drop the components into QSYS, click the little dots in the 'Connections' column to wire them together. The grey outlines will go black once the connections are made and the errors will be cleared.

You will be greatly aided by completing the Qsys tutorials available at Altera.com, support section, search for OQSYS1000.