Electronic – Dual JK Flip-Flop Toogle Feature

Provocative question: have you tried googling for Flip-flop D counter? I found this.

The trick is that if you feed back the inverted output of the flip flop to the input, you get a circuit that divides the clock frequency by two.

The principle is not that hard to grasp. The flip flop D replicates the D input to the output Q when the clock rises. The inverted output is the opposite: if you connect it to the input, at every clock cycle the input will get inverted, and thus the output. This happens at every rising edge, so every two clock edges (rising and falling) you have one output edge (rising or falling).

Cascading three flip flops and taking their outputs as the three bits of the value, you get a base-8 counter. You can see that from the truth table: Q0 changes at every count, Q1 every two and so forth.

It's hard (impossible?) to describe the behavior with just truth tables, but basically D0=Q0', D1=Q1' and D2=Q2'. Then, CLK1=Q0 and CLK2=Q1.

The inversion of input is because the NAND inputs are active (forcing the output) when low, and NOR inputs are active (forcing the output) when high. The current state is needed in the truth table as the next state may depend on both the current state and the inputs.

If you look at both outputs of an SR-latch, an active Set will override the output value of the gate Set is connected to. The same applies to reset, e.g. an active Reset will override the output value of the gate it is connected to. If you put both Set and Reset in the 'illegal' condition where both are active, you force both outputs to "00" for a NOR latch and to "11" for a NAND latch.

If both input signals start from the 'illegal' condition (both S and R active) you can create an arbiter circuit. When one of the inputs now goes inactive, the SR latch will remember which input was first to go inactive, for as long as the first input stays inactive. That can for instance be useful to arbitrate between multiple circuits utilizing a bus in an asynchronous design.

However for digital, sequential design the normal use of the SR-latch is to remember one of two previous and volatile states (not three as in the arbiter), thus you need to be careful about not setting both Set and Reset active at the same time, as then your final output will be determined by which of the inputs go inactive first. E.g. if both Set and Reset go inactive at the same clock edge, you have very little control over what state you end up in.

For nearly simultaneous transitions on both Set and Reset (for the SR transitions "10"=>"01", "01"=>"10", and "11"=>"00") you may enter a meta-stable state, where for a duration the output is neither '0' nor '1'. This pretty much means that you cannot determine how it will affect the gate(s) it is driving. Given enough time the metastable state will correct itself due to noise, but you don't know to which value. (In an arbiter you might not care about which way it goes, however you should design to keep a possible metastability event short&small enough to avoid producing an "acknowledge" that you end up retracting. This may not be possible unless you are doing a full custom design, and can be hard even then.).