Electronic – FIltering ADC input

Some observations:

1. The two middle opamps don't have power. Opamps need power to function according to spec.

2. Actually after Steven's comment I see all 4 opamps are in a single package, which apparently is powered. The problem is therefore one of bad schematic drawing. When you have multiple parts in a single package with common power like this, usually you show the power pins as a separate schematic part, like U13E for example. You can show the power and ground pins on one of the four opamps, but that can add clutter and makes that amp look more special than the others. However, never do what you did, which is to show the power and ground pins on each schematic part.

   Even worse, you then showed two of the parts with power and ground connected, and two without. What if the two pairs were connected to different power and ground voltages? That would be really misleading since it's not physically possible. This kind of schematic convention makes no sense and invites exactly the kind of confusion shown in point 1 above. I left that there so you can see what the first reaction to this misleading schematic was.

3. There is no bypass cap anywhere accross the opamp power pins.

4. You don't say what voltage Vcc is. The TL084 needs a few volts headroom from each power rail, so Vcc should be at least the largest signal voltage plus the headroom.

5. 220 Ω seems very small for R33. Can the TL084 really drive that much current (I haven't checked)? Even if it can, why is that necessary?

6. With D13 in series with R33, Vdetect will be undriven (high impedance) when the opamp goes low. Is this really what you want?

7. D17 shouldn't be right on the output of U13C. That will violate the max output current source capability of the opamp when it is trying to drive high.

That is correct.

A capacitor is needed because such ADC are SAR and as such the switching can cause an upset to the part in question. Typically a SAR type ADC requires any input pin capacitance to be a minimum of 10x the Cia to ensure that when it switches the actual voltage on the input pin does not droop (before said capacitance can be trickle charged from any sensor).

4.7nF satisfies this and is a typical value I would use when connecting Allegro devices directly to an ADC. The only times I consider placing a buffer between the Allegro and an ADC is if I require a larger capacitance (usually due to filter time constant concerns)

Not to sure about explicitly placing an Rl in parallel with the sensor, in series with the output to produce an RC filter may be of more benefit

Once piece of advice. The benefit of these devices over others is their ratiometric gain w.r.t. supply voltage. Ensure such a device is as physically close to the ADC as possible to ensure the ADC and the HES share the same rail so the ratiometric nature of the ADC & HES can be taken advantage of (by same rail I don't mean 5V powerplane on a 1m x 1m PCB... I mean their power pins as close as a via and decent local tracing will allow)