Odd vs Even Parity
This will depend slightly on what communication you are using. I know you said you are using UART, but I am going to answer a bit broader. If you do decide to go with parity, select the option that will cause your "idle" state to require the parity bit to switch.
If you have an active high system, then all 0's is idle. So make it odd parity so that the parity bit will have to change state from idle.
In an active low system you should look at how many bits the parity will be over. If it is 8 bits, then even parity will result in a 0 parity bit, which follows the idea of forcing a change in state for the parity.
Should you use Parity?
Well this is a bit of a difficult questions. In general we like to model the noise as Gaussian noise which means that the bit errors will be completely random. In actuality noise that has an effect on our system is not always random. The reason for this is things that can cause errors on a PCB are radiators from something else. If you think about it, in order for a trace that short to have enough noise to cause bit error then it had to be something rather extreme. When you have a noise source like this, there is a decent chance that you will flip more then one bit. Parity is useless against an even number of bit errors. With out diving into the math, parity will help, but doesn't help tons. If you can't afford to do much processing then parity may be the best that you can do..
Why use a CRC?
First of all, you say you have a built in CRC generator, this means it should be very easy for you to compute. CRCs are much better at catching multiple bit errors. In an environment where you want a very low chance of getting any errors, you really want to use a CRC. In fact, go with the biggest CRC you can afford in your system. One little trick that I know works for atleast crc16 if not others is if you CRC the message you received with the CRC on it you should get 0 as your answer. If you have hardware to compute the CRC then this is a very efficient way of both generating CRC and checking CRC.
The parity and number of bits transmitted are controlled by the configuration of the UART (Universal Asynchronous Receiver/Transmitter) device in each piece of equipment. This component converts the data written to it in (usually) byte parallel format to the data bitstream that is sent serially between the client and server (in your example).
To transmit in 7E1 the UART is configured to ignore the MSB and then to add the parity bit as the last bit of data transmitted giving 8 transmitted data bits. In 8N1 the UART transmits the 8 data bits. By convention the data is transmitted LSB first.
Looking at your data I would suspect that where you have written B you really mean 8 (this would fit with the data transmission modes specified).
When transmitting the data over a 7E1 link then the 8 bits transmitted for your data will be
Data Parity Transmitted byte
06 0 0x06
02 1 0x82
05 0 0x05
02 1 0x82
0D 1 0x8D
0A 0 0x0A
Are the three middle bytes ASCII representations of the values that you have declared in your question (2 ->0x32, 5->0x35 )? If this is the case than the data received will match the data transmitted with the addition of a parity bit.
Data Parity Transmitted byte
06 0 0x06
32 1 0xB2
35 0 0x35
32 1 0xB2
0D 1 0x8D
0A 0 0x0A
Best Answer
A parity bit is used to detect single bit errors in a data stream. It does this by adding an extra bit, the parity bit. This bit is set to a value to ensure that the number of 1's in a word is even. So if there is an odd number of 1's in the data stream, the parity bit would be 1. If there are an even number already, the parity bit would be 0.
It makes no difference whether there are an even or odd number of bits in the data word, as the parity bit is counting the number of 1's, not the number of bits.
Some examples:
3 data bits + 1 parity bit
6 data bits + 1 parity bit
Notice how the parity bit ensures that there is an even number of 1's in every one of those words. In fact it works for any word of any length.
How is it calculated?
Quite simply actually. It is basically the bit sum of every bit in the stream, modulo 2. So you add each bit in turn, doing modulo 2 after each sum (*). This results in either a 0 or 1 which is the parity bit.
(*) You can actually do it at after summing all the bits if you want.