Wikipedia's Instructions per second page says that an i7 3630QM deliver ~110,000 MIPS at a frequency of 3.2 GHz; it would be (110/3.2 instructions) / 4 core = ~8.6 instructions per cycle per core?!
How can a single core deliver more than one instruction per cycle?
To my understanding a pipeline should only be able to deliver one result per clock.
These are my thoughts:
- Internal frequency is actually higher than 3.2 GHz
- Some parts of the CPU are asynchronous in a way a humble human like myself cannot understand
- There are multiple concurrent pipelines per core
- A pipeline can deliver more than result per clock, an instruction can skip pipeline stages and there are multiple prefetcher to keep up
- I am missing something